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Commit 997921ee authored by joachim.schmidt's avatar joachim.schmidt
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Updated firmware design "scalp_firmware" with back pressure management for each receiving fifo.

parent 2b34341c
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with 474 additions and 110 deletions
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Cleanup project directory # Description: Cleanup project directory
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware' # Description: TCL script for re-creating Vivado project 'scalp_firmware'
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
...@@ -72,8 +72,14 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -72,8 +72,14 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc] set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
#add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file # add IPs source file
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd] set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list { foreach j $vhdl_ips_file_list {
...@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
...@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list { ...@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list {
print_status "VHDL 2008 mode configured for testbench sources" "OK" print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources # Add packages sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list { foreach j $vhdl_pkg_file_list {
...@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
}
print_status "Add packages sources" "OK" print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK" print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files # Add SoC wrapper sources files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd] set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list { foreach j $vhdl_soc_file_list {
...@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
}
print_status "Add SoC wrapper sources" "OK" print_status "Add SoC wrapper sources" "OK"
print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK" print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate bitstream file # Description: Generate bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate bitstream file # Description: TCL script used to generate bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate software application # Description: Generate software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate software application # Description: TCL script used to generate software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load bitstream file # Description: Load bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream # Description: TCL script used to load FPGA bitstream
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load software application # Description: Load software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load software application # Description: TCL script used to load software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Project management utilities # Description: Project management utilities
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts # Description: TCL script creating aliases for Vivado project management scripts
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2019.2 -- Tool version: 2019.2
-- Description: Testbench for scalp_firmware -- Description: Testbench for scalp_firmware
-- --
-- Last update: 2020-10-13 13:10:02 -- Last update: 2020-11-07 09:14:14
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
......
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