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Commit 9d871090 authored by joachim.schmidt's avatar joachim.schmidt
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Update scalp_firmware for testing.

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designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+ 15
− 34
View file @ 9d871090
......@@ -526,10 +526,10 @@ architecture arch of scalp_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
attribute mark_debug of WestRXM2SxD : signal is "true";
attribute keep of WestRXM2SxD : signal is "true";
attribute mark_debug of WestRXS2MxD : signal is "true";
attribute keep of WestRXS2MxD : signal is "true";
attribute mark_debug of WestRXM2SxD : signal is "true";
attribute keep of WestRXM2SxD : signal is "true";
attribute mark_debug of WestRXS2MxD : signal is "true";
attribute keep of WestRXS2MxD : signal is "true";
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-- attribute keep of RXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
......@@ -872,7 +872,7 @@ begin
-- type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID, E_WR_SP_WAIT);
type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_UNVALID_0, E_WR_SP_VALID_1, E_WR_SP_WAIT);
type t_write_sp_states is (E_WR_SP_IDLE, E_WR_SP_VALID_0, E_WR_SP_LAST, E_WR_SP_VALID_1, E_WR_SP_WAIT);
signal ScalpRouterResetxRNA : std_ulogic := '0';
-- Scalp Packets
......@@ -1133,7 +1133,8 @@ begin
end if;
end process UpdateRegxP;
SpValidxP : process (VioWrSpValidxS, WrSPStatexDP) is
SpValidxP : process (RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS,
VioWrSpValidxS, WrSPStatexDP) is
begin -- process SpValidxP
-- Default values
WrSPStatexDN <= WrSPStatexDP;
......@@ -1145,46 +1146,26 @@ begin
ScalpPacketValid12xS <= '1';
WrSPStatexDN <= E_WR_SP_VALID_0;
end if;
when E_WR_SP_VALID_0 =>
ScalpPacketValid12xS <= '0';
WrSPStatexDN <= E_WR_SP_UNVALID_0;
WrSPStatexDN <= E_WR_SP_LAST;
when E_WR_SP_UNVALID_0 =>
ScalpPacketValid12xS <= '1';
WrSPStatexDN <= E_WR_SP_VALID_1;
when E_WR_SP_LAST =>
if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
ScalpPacketValid12xS <= '1';
WrSPStatexDN <= E_WR_SP_VALID_1;
end if;
when E_WR_SP_VALID_1 =>
ScalpPacketValid12xS <= '0';
WrSPStatexDN <= E_WR_SP_WAIT;
-- when E_WR_SP_WAIT_0 =>
-- WrSPStatexDN <= E_WR_SP_IDLE_1;
-- when E_WR_SP_IDLE_1 =>
-- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '1' then
-- WrSPStatexDN <= E_WR_LAST_1;
-- ScalpPacketValid12xS <= '1';
-- end if;
-- when E_WR_LAST_1 =>
-- if RXAxism2sVectorxD(C_LOCAL_IF_ID).LastxS = '0' then
-- -- ScalpPacketValid12xS <= '1';
-- ScalpPacketValid12xS <= '0';
-- -- WrSPStatexDN <= E_WR_SP_VALID_1;
-- WrSPStatexDN <= E_WR_SP_WAIT_1;
-- end if;
-- -- when E_WR_SP_VALID_1 =>
-- -- ScalpPacketValid12xS <= '0';
-- -- WrSPStatexDN <= E_WR_SP_WAIT_1;
when E_WR_SP_WAIT =>
if VioWrSpValidxS = '0' then
WrSPStatexDN <= E_WR_SP_IDLE;
end if;
-- if VioWrSpValidxS = '0' then
-- WrSPStatexDN <= E_WR_SP_IDLE;
-- end if;
when others => null;
end case;
end process SpValidxP;
......
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