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Commit aefc3150 authored by joachim.schmidt's avatar joachim.schmidt
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Creation of the IP core scalp_axilite and IP packaging for integration in a Zynq SoC.

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ips/hw/scalp_axi4lite/component.xml 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>hepia.hesge.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_axi4lite</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>InterruptxSI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>InterruptxSI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>InterruptxSO</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>InterruptxSO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>SAxiClkxCI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiClkxCI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.FREQ_HZ"/>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_RESET">SAxiResetxRANI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SAXICLKXCI.ASSOCIATED_BUSIF">SAXILitexDIO</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
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<spirit:name>SAxiResetxRANI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:name>SAxiResetxRANI</spirit:name>
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<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
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<spirit:name>SAXILitexDIO</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
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<spirit:memoryMapRef spirit:memoryMapRef="SAXILitexDIO"/>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
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<spirit:name>SAxiWStrbxDI</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
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<spirit:name>SAxiBRespxDO</spirit:name>
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<spirit:name>RDATA</spirit:name>
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<spirit:name>SAxiRDataxDO</spirit:name>
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<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
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<spirit:name>SAXILitexDIO</spirit:name>
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<spirit:displayName>SAXILiteAddr</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>VHDL-2008</spirit:language>
<spirit:modelName>scalp_axi4lite</spirit:modelName>
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<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AXI4_DATA_SIZE">32</spirit:value>
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ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd 0 → 100644
+ 229
− 0
View file @ aefc3150
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: scalp_axi4lite - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: scalp_axi4lite
--
-- Last update: 2020-11-08
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity scalp_axi4lite is
generic (
C_AXI4_ARADDR_SIZE : integer := 32;
C_AXI4_RDATA_SIZE : integer := 32;
C_AXI4_RRESP_SIZE : integer := 2;
C_AXI4_AWADDR_SIZE : integer := 32;
C_AXI4_WDATA_SIZE : integer := 32;
C_AXI4_WSTRB_SIZE : integer := 4;
C_AXI4_BRESP_SIZE : integer := 2;
C_AXI4_DATA_SIZE : integer := 32;
C_AXI4_ADDR_SIZE : integer := 12);
port (
-- Clock and Reset
SAxiClkxCI : in std_logic;
SAxiResetxRANI : in std_logic;
-- Write Channel
-- Write Address Channel
SAxiAWAddrxDI : in std_logic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_logic;
SAxiAWReadyxSO : out std_logic;
-- Write Data Channel
SAxiWDataxDI : in std_logic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_logic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_logic;
SAxiWReadyxSO : out std_logic;
-- Write Response Channel
SAxiBRespxDO : out std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_logic;
SAxiBReadyxSI : in std_logic;
-- Read Channel
-- Read Address Channel
SAxiARAddrxDI : in std_logic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_logic;
SAxiARReadyxSO : out std_logic;
-- Read Data Channel
SAxiRDataxDO : out std_logic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_logic;
SAxiRReadyxSI : in std_logic;
-- Signal for Writing in a Register Bank
WrDataxDO : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
WrAddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
WrValidxSO : out std_logic;
-- Signal for Reading in a Register Bank
RdDataxDI : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
RdAddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
RdValidxSO : out std_logic;
-- Interrupt Interface
InterruptxSI : in std_logic;
InterruptxSO : out std_logic);
end scalp_axi4lite;
architecture arch of scalp_axi4lite is
-- Components
component scalp_axi4lite_wr_chan is
generic (
C_AXI4_AWADDR_SIZE : integer;
C_AXI4_WDATA_SIZE : integer;
C_AXI4_WSTRB_SIZE : integer;
C_AXI4_BRESP_SIZE : integer;
C_AXI4_DATA_SIZE : integer;
C_AXI4_ADDR_SIZE : integer);
port (
-- Clock and Reset
SAxiClkxCI : in std_logic;
SAxiResetxRANI : in std_logic;
-- Write Address Channel
SAxiAWAddrxDI : in std_logic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_logic;
SAxiAWReadyxSO : out std_logic;
-- Write Data Channel
SAxiWDataxDI : in std_logic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_logic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_logic;
SAxiWReadyxSO : out std_logic;
-- Write Response Channel
SAxiBRespxDO : out std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_logic;
SAxiBReadyxSI : in std_logic;
-- Signal for Writing in a Register Bank
DataxDO : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
AddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
ValidxSO : out std_logic);
end component scalp_axi4lite_wr_chan;
component scalp_axi4lite_rd_chan is
generic (
C_AXI4_ARADDR_SIZE : integer;
C_AXI4_RDATA_SIZE : integer;
C_AXI4_RRESP_SIZE : integer;
C_AXI4_DATA_SIZE : integer;
C_AXI4_ADDR_SIZE : integer);
port (
SAxiClkxCI : in std_logic;
SAxiResetxRANI : in std_logic;
SAxiARAddrxDI : in std_logic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_logic;
SAxiARReadyxSO : out std_logic;
SAxiRDataxDO : out std_logic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_logic;
SAxiRReadyxSI : in std_logic;
DataxDI : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
AddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
ValidxSO : out std_logic);
end component scalp_axi4lite_rd_chan;
begin -- architecture rtl
-- Asynchronous statements
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
report "RDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
report "ARADDR and ADDR vectors must be the same" severity failure;
assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
report "WDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
InterruptxB : block is
begin -- block InterruptxB
InterruptxSO <= InterruptxSI;
end block InterruptxB;
-- Synchronous statements
ScalpAxi4LitexB : block is
begin -- block ScalpAxi4LitexB
ScalpAxi4LiteWrChanxI : entity work.scalp_axi4lite_wr_chan
generic map (
C_AXI4_AWADDR_SIZE => C_AXI4_AWADDR_SIZE,
C_AXI4_WDATA_SIZE => C_AXI4_WDATA_SIZE,
C_AXI4_WSTRB_SIZE => C_AXI4_WSTRB_SIZE,
C_AXI4_BRESP_SIZE => C_AXI4_BRESP_SIZE,
C_AXI4_DATA_SIZE => C_AXI4_DATA_SIZE,
C_AXI4_ADDR_SIZE => C_AXI4_ADDR_SIZE)
port map (
-- Clock and Reset
SAxiClkxCI => SAxiClkxCI,
SAxiResetxRANI => SAxiResetxRANI,
-- Write Address Channel
SAxiAWAddrxDI => SAxiAWAddrxDI,
SAxiAWValidxSI => SAxiAWValidxSI,
SAxiAWReadyxSO => SAxiAWReadyxSO,
-- Write Data Channel
SAxiWDataxDI => SAxiWDataxDI,
SAxiWStrbxDI => SAxiWStrbxDI,
SAxiWValidxSI => SAxiWValidxSI,
SAxiWReadyxSO => SAxiWReadyxSO,
-- Write Response Channel
SAxiBRespxDO => SAxiBRespxDO,
SAxiBValidxSO => SAxiBValidxSO,
SAxiBReadyxSI => SAxiBReadyxSI,
-- Signal for Writing in a Register Bank
DataxDO => WrDataxDO,
AddrxDO => WrAddrxDO,
ValidxSO => WrValidxSO);
ScalpAxi4LiteRdChanxI : entity work.scalp_axi4lite_rd_chan
generic map (
C_AXI4_ARADDR_SIZE => C_AXI4_ARADDR_SIZE,
C_AXI4_RDATA_SIZE => C_AXI4_RDATA_SIZE,
C_AXI4_RRESP_SIZE => C_AXI4_RRESP_SIZE,
C_AXI4_DATA_SIZE => C_AXI4_DATA_SIZE,
C_AXI4_ADDR_SIZE => C_AXI4_ADDR_SIZE)
port map (
-- Clock and Reset
SAxiClkxCI => SAxiClkxCI,
SAxiResetxRANI => SAxiResetxRANI,
-- Read Address Channel
SAxiARAddrxDI => SAxiARAddrxDI,
SAxiARValidxSI => SAxiARValidxSI,
SAxiARReadyxSO => SAxiARReadyxSO,
-- Read Data Channel
SAxiRDataxDO => SAxiRDataxDO,
SAxiRRespxDO => SAxiRRespxDO,
SAxiRValidxSO => SAxiRValidxSO,
SAxiRReadyxSI => SAxiRReadyxSI,
-- Signal for Reading in a Register Bank
DataxDI => RdDataxDI,
AddrxDO => RdAddrxDO,
ValidxSO => RdValidxSO);
end block ScalpAxi4LitexB;
end arch;
ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd 0 → 100644
+ 198
− 0
View file @ aefc3150
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: scalp_axi4lite_rd_chan - behavioural
-- Target Device: All
-- Tool version: 2019.2
-- Description: AXI4 Lite Read Channel Slave Side
--
-- Last update: 2020-11-08
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity scalp_axi4lite_rd_chan is
generic (
C_AXI4_ARADDR_SIZE : integer := 32;
C_AXI4_RDATA_SIZE : integer := 32;
C_AXI4_RRESP_SIZE : integer := 2;
C_AXI4_DATA_SIZE : integer := 32;
C_AXI4_ADDR_SIZE : integer := 12);
port (
-- Clock and Reset
SAxiClkxCI : in std_logic;
SAxiResetxRANI : in std_logic;
-- Read Address Channel
SAxiARAddrxDI : in std_logic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_logic;
SAxiARReadyxSO : out std_logic;
-- Read Data Channel
SAxiRDataxDO : out std_logic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_logic;
SAxiRReadyxSI : in std_logic;
-- Signal for Reading in a Register Bank
DataxDI : in std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
AddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
ValidxSO : out std_logic);
end entity scalp_axi4lite_rd_chan;
architecture behavioural of scalp_axi4lite_rd_chan is
-- Constants
constant C_AXI4_RRESP_OKAY : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_RRESP_EXOKAY : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_RRESP_SLVERR : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_RRESP_DECERR : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
-- Signals
signal SAxiARReadyxS : std_logic := '0';
signal SAxiRValidxS : std_logic := '0';
-- signal SAxiRDataxD : std_logic_vector((C_AXI4_RDATA_SIZE - 1) downto 0) := (others => '0');
-- signal SAxiRRespxD : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := C_AXI4_RRESP_OKAY;
begin -- architecture behavioural
-- Asynchronous statements
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
report "RDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
report "ARADDR and ADDR vectors must be the same" severity failure;
-- DebugxB : block is
-- -- Debug Signals
-- signal DebugSAxiARAddrxD : std_logic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiARValidxS : std_logic := '0';
-- signal DebugSAxiARReadyxS : std_logic := '0';
-- signal DebugSAxiRDataxD : std_logic_vector((C_AXI4_RDATA_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiRRespxD : std_logic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiRValidxS : std_logic := '0';
-- signal DebugSAxiRReadyxS : std_logic := '0';
-- signal DebugRdDataxD : std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- signal DebugRdAddrxD : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- signal DebugRdValidxS : std_logic := '0';
-- -- Debug Attributes
-- -- Attributes Declaration
-- attribute keep : string;
-- attribute mark_debug : string;
-- -- Attributes Specification
-- attribute keep of DebugSAxiARAddrxD : signal is "true";
-- attribute mark_debug of DebugSAxiARAddrxD : signal is "true";
-- attribute keep of DebugSAxiARValidxS : signal is "true";
-- attribute mark_debug of DebugSAxiARValidxS : signal is "true";
-- attribute keep of DebugSAxiARReadyxS : signal is "true";
-- attribute mark_debug of DebugSAxiARReadyxS : signal is "true";
-- attribute keep of DebugSAxiRDataxD : signal is "true";
-- attribute mark_debug of DebugSAxiRDataxD : signal is "true";
-- attribute keep of DebugSAxiRRespxD : signal is "true";
-- attribute mark_debug of DebugSAxiRRespxD : signal is "true";
-- attribute keep of DebugSAxiRValidxS : signal is "true";
-- attribute mark_debug of DebugSAxiRValidxS : signal is "true";
-- attribute keep of DebugSAxiRReadyxS : signal is "true";
-- attribute mark_debug of DebugSAxiRReadyxS : signal is "true";
-- attribute keep of DebugRdDataxD : signal is "true";
-- attribute mark_debug of DebugRdDataxD : signal is "true";
-- attribute keep of DebugRdAddrxD : signal is "true";
-- attribute mark_debug of DebugRdAddrxD : signal is "true";
-- attribute keep of DebugRdValidxS : signal is "true";
-- attribute mark_debug of DebugRdValidxS : signal is "true";
-- begin -- block DebugxB
-- DebugSAxiARAddrxAS : DebugSAxiARAddrxD <= SAxiARAddrxDI;
-- DebugSAxiARValidxAS : DebugSAxiARValidxS <= SAxiARValidxSI;
-- DebugSAxiARReadyxAS : DebugSAxiARReadyxS <= SAxiARReadyxS;
-- DebugSAxiRDataxAS : DebugSAxiRDataxD <= DataxDI;
-- DebugSAxiRRespxAS : DebugSAxiRRespxD <= C_AXI4_RRESP_OKAY;
-- DebugSAxiRValidxAS : DebugSAxiRValidxS <= SAxiRValidxS;
-- DebugSAxiRReadyxAS : DebugSAxiRReadyxS <= SAxiRReadyxSI;
-- DebugDataxAS : DebugRdDataxD <= DataxDI;
-- DebugAddrxAS : DebugRdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
-- DebugValidxAS : DebugRdValidxS <= SAxiARValidxSI;
-- end block DebugxB;
IOEntityxB : block is
begin -- block IOEntityxB
SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
SAxiRDataxAS : SAxiRDataxDO <= DataxDI;
ValidxAS : ValidxSO <= SAxiARValidxSI; --
--SAxiRValidxS;
AddrxAS : AddrxDO((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
end block IOEntityxB;
-- Synchronous statements
ReadAddrChanxP : process (SAxiClkxCI, SAxiResetxRANI) is
variable StateAfterResetxS : boolean := true;
begin -- process ReadAddrChanxP
if SAxiResetxRANI = '0' then
SAxiARReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxCI) then
if StateAfterResetxS = true then
SAxiARReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiARReadyxS <= SAxiARReadyxS;
end if;
if SAxiARValidxSI = '1' then
SAxiARReadyxS <= '0';
end if;
if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
SAxiARReadyxS <= '1';
end if;
end if;
end process ReadAddrChanxP;
ReadDataChanxP : process (SAxiClkxCI, SAxiResetxRANI) is
begin -- process ReadDataChanxP
if SAxiResetxRANI = '0' then
SAxiRValidxS <= '0';
elsif rising_edge(SAxiClkxCI) then
SAxiRValidxS <= SAxiRValidxS;
if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
SAxiRValidxS <= '1';
end if;
if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
SAxiRValidxS <= '0';
end if;
end if;
end process ReadDataChanxP;
end architecture behavioural;
ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd 0 → 100644
+ 247
− 0
View file @ aefc3150
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: scalp_axi4lite_wr_chan - behavioural
-- Target Device: All
-- Tool version: 2019.2
-- Description: AXI4 Lite Write Channel Slave Side
--
-- Last update: 2020-11-08
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity scalp_axi4lite_wr_chan is
generic (
C_AXI4_AWADDR_SIZE : integer := 32;
C_AXI4_WDATA_SIZE : integer := 32;
C_AXI4_WSTRB_SIZE : integer := 4;
C_AXI4_BRESP_SIZE : integer := 2;
C_AXI4_DATA_SIZE : integer := 32;
C_AXI4_ADDR_SIZE : integer := 12);
port (
-- Clock and Reset
SAxiClkxCI : in std_logic;
SAxiResetxRANI : in std_logic;
-- Write Address Channel
SAxiAWAddrxDI : in std_logic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_logic;
SAxiAWReadyxSO : out std_logic;
-- Write Data Channel
SAxiWDataxDI : in std_logic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_logic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_logic;
SAxiWReadyxSO : out std_logic;
-- Write Response Channel
SAxiBRespxDO : out std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_logic;
SAxiBReadyxSI : in std_logic;
-- Signal for Writing in a Register Bank
DataxDO : out std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
AddrxDO : out std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0);
ValidxSO : out std_logic);
end entity scalp_axi4lite_wr_chan;
architecture behavioural of scalp_axi4lite_wr_chan is
-- Constants
constant C_AXI4_BRESP_OKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_BRESP_EXOKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_BRESP_SLVERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_BRESP_DECERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
-- Signals
-- signal SAxiBRespxD : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := (others => '0');
signal SAxiBValidxS : std_logic := '0';
signal SAxiWReadyxS : std_logic := '0';
signal SAxiAWReadyxS : std_logic := '0';
signal AddrxDN : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal AddrxDP : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
begin -- architecture behavioural
-- Asynchronous statements
assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
report "WDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
-- DebugxB : block is
-- -- Debug Signals
-- signal DebugSAxiAWAddrxD : std_logic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiAWValidxS : std_logic := '0';
-- signal DebugSAxiAWReadyxS : std_logic := '0';
-- signal DebugSAxiWDataxD : std_logic_vector((C_AXI4_WDATA_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiWStrbxD : std_logic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiWValidxS : std_logic := '0';
-- signal DebugSAxiWReadyxS : std_logic := '0';
-- signal DebugSAxiBRespxD : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := (others => '0');
-- signal DebugSAxiBValidxS : std_logic := '0';
-- signal DebugSAxiBReadyxS : std_logic := '0';
-- signal DebugWrDataxD : std_logic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- signal DebugWrAddrxD : std_logic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- signal DebugWrValidxS : std_logic := '0';
-- -- Debug Attributes
-- -- Attributes Declaration
-- attribute keep : string;
-- attribute mark_debug : string;
-- -- Attributes Specification
-- attribute keep of DebugSAxiAWAddrxD : signal is "true";
-- attribute mark_debug of DebugSAxiAWAddrxD : signal is "true";
-- attribute keep of DebugSAxiAWValidxS : signal is "true";
-- attribute mark_debug of DebugSAxiAWValidxS : signal is "true";
-- attribute keep of DebugSAxiAWReadyxS : signal is "true";
-- attribute mark_debug of DebugSAxiAWReadyxS : signal is "true";
-- attribute keep of DebugSAxiWDataxD : signal is "true";
-- attribute mark_debug of DebugSAxiWDataxD : signal is "true";
-- attribute keep of DebugSAxiWStrbxD : signal is "true";
-- attribute mark_debug of DebugSAxiWStrbxD : signal is "true";
-- attribute keep of DebugSAxiWValidxS : signal is "true";
-- attribute mark_debug of DebugSAxiWValidxS : signal is "true";
-- attribute keep of DebugSAxiWReadyxS : signal is "true";
-- attribute mark_debug of DebugSAxiWReadyxS : signal is "true";
-- attribute keep of DebugSAxiBRespxD : signal is "true";
-- attribute mark_debug of DebugSAxiBRespxD : signal is "true";
-- attribute keep of DebugSAxiBValidxS : signal is "true";
-- attribute mark_debug of DebugSAxiBValidxS : signal is "true";
-- attribute keep of DebugSAxiBReadyxS : signal is "true";
-- attribute mark_debug of DebugSAxiBReadyxS : signal is "true";
-- attribute keep of DebugWrDataxD : signal is "true";
-- attribute mark_debug of DebugWrDataxD : signal is "true";
-- attribute keep of DebugWrAddrxD : signal is "true";
-- attribute mark_debug of DebugWrAddrxD : signal is "true";
-- attribute keep of DebugWrValidxS : signal is "true";
-- attribute mark_debug of DebugWrValidxS : signal is "true";
-- begin -- block DebugxB
-- DebugSAxiAWAddrxAS : DebugSAxiAWAddrxD <= SAxiAWAddrxDI;
-- DebugSAxiAWValidxAS : DebugSAxiAWValidxS <= SAxiAWValidxSI;
-- DebugSAxiAWReadyxAS : DebugSAxiAWReadyxS <= SAxiAWReadyxS;
-- DebugSAxiWDataxAS : DebugSAxiWDataxD <= SAxiWDataxDI;
-- DebugSAxiWStrbxAS : DebugSAxiWStrbxD <= SAxiWStrbxDI;
-- DebugSAxiWValidxAS : DebugSAxiWValidxS <= SAxiWValidxSI;
-- DebugSAxiWReadyxAS : DebugSAxiWReadyxS <= SAxiWReadyxS;
-- DebugSAxiBRespxAS : DebugSAxiBRespxD <= C_AXI4_BRESP_OKAY;
-- DebugSAxiBValidxAS : DebugSAxiBValidxS <= SAxiBValidxS;
-- DebugSAxiBReadyxAS : DebugSAxiBReadyxS <= SAxiBReadyxSI;
-- DebugWrDataxAS : DebugWrDataxD <= SAxiWDataxDI;
-- DebugWrAddrxAS : DebugWrAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= AddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
-- DebugWrValidxAS : DebugWrValidxS <= SAxiWValidxSI;
-- end block DebugxB;
IOEntityxB : block is
begin -- block IOEntityxB
SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
ValidxAS : ValidxSO <= SAxiWValidxSI;
DataxAS : DataxDO <= SAxiWDataxDI;
AddrOutxAS : AddrxDO <= AddrxDP;
AddrxAS : AddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
SAxiAWValidxSI = '1' else
AddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
-- AddrxAS : AddrxDO((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
end block IOEntityxB;
-- Synchronous statements
AddrRegxP : process (SAxiClkxCI, SAxiResetxRANI) is
begin -- process AddrRegxP
if SAxiResetxRANI = '0' then
AddrxDP <= (others => '0');
elsif rising_edge(SAxiClkxCI) then
AddrxDP <= AddrxDN;
end if;
end process AddrRegxP;
WriteAddrChanxP : process (SAxiClkxCI, SAxiResetxRANI) is
variable StateAfterResetxS : boolean := true;
begin -- process WriteAddrChanxP
if SAxiResetxRANI = '0' then
SAxiAWReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxCI) then
if StateAfterResetxS = true then
SAxiAWReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiAWReadyxS <= SAxiAWReadyxS;
end if;
if SAxiAWValidxSI = '1' then
SAxiAWReadyxS <= '0';
end if;
if SAxiWValidxSI = '1' then
SAxiAWReadyxS <= '1';
end if;
end if;
end process WriteAddrChanxP;
WriteDataChanxP : process (SAxiClkxCI, SAxiResetxRANI) is
begin -- process WriteDataChanxP
if SAxiResetxRANI = '0' then
SAxiWReadyxS <= '0';
elsif rising_edge(SAxiClkxCI) then
SAxiWReadyxS <= SAxiWReadyxS;
if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
SAxiWReadyxS <= '1';
end if;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiWReadyxS <= '0';
end if;
end if;
end process WriteDataChanxP;
WriteRespChanxP : process (SAxiClkxCI, SAxiResetxRANI) is
begin -- process WriteRespChanxP
if SAxiResetxRANI = '0' then
SAxiBValidxS <= '0';
elsif rising_edge(SAxiClkxCI) then
SAxiBValidxS <= SAxiBValidxS;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiBValidxS <= '1';
end if;
if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
SAxiBValidxS <= '0';
end if;
end if;
end process WriteRespChanxP;
end architecture behavioural;
ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd 0 → 100644
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----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_axi4lite - arch
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2019.2
-- Description: Testbench for scalp_axi4lite
--
-- Last update: 2020-11-08 07:53:10
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_scalp_axi4lite is
end tb_scalp_axi4lite;
architecture behavioral of tb_scalp_axi4lite is
begin
end behavioral;
ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_0.tcl 0 → 100644
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/.prompt_colors.tcl 0 → 100644
+ 37
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Console color print utility
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh 0 → 100755
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#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Cleanup project directory
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_axi4lite/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.sh 0 → 100755
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− 0
View file @ aefc3150
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_scalp_axi4lite.tcl -notrace
echo "> Done"
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl 0 → 100644
+ 154
− 0
View file @ aefc3150
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_axi4lite'
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_axi4lite"
set PKG_DIR "${PRJ_DIR}/../../../../../packages"
set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw"
set soc_src_dir "${SOC_DIR}/hw"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
#set_property board_part SCALP [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source file
#read_ip $src_dir/custom_ip/ip_0/ip_0.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
#read_ip $comp_src_dir/ip_core/ip_0/ip_0.xci
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
#----------------------------------------------------------------
# Add constraints files
#----------------------------------------------------------------
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/open_prj_scalp_axi4lite.sh 0 → 100755
+ 25
− 0
View file @ aefc3150
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Create Vivado project
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
echo "> Open Vivado GUI..."
vivado -nojournal -nolog -notrace ../scalp_axi4lite/scalp_axi4lite.xpr
ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/utils.tcl 0 → 100644
+ 62
− 0
View file @ aefc3150
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: Project management utilities
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
# findFiles
# basedir - the directory to start looking in
# pattern - A pattern, as defined by the glob command, that the files must match
proc findFiles { basedir pattern } {
# Fix the directory name, this ensures the directory name is in the
# native format for the platform and contains a final directory seperator
set basedir [string trimright [file join [file normalize $basedir] { }]]
set fileList {}
# Look in the current directory for matching files, -type {f r}
# means ony readable normal files are looked at, -nocomplain stops
# an error being thrown if the returned list is empty
foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
lappend fileList $fileName
}
# Now look for any sub direcories in the current directory
foreach dirName [glob -nocomplain -type {d r} -path $basedir *] {
# Recusively call the routine on the sub directory and append any
# new files to the results
set subDirList [findFiles $dirName $pattern]
if { [llength $subDirList] > 0 } {
foreach subDirFile $subDirList {
lappend fileList $subDirFile
}
}
}
return $fileList
}
# Print a progress status
# str The string describing the current status
# status The status as a string (eg. "OK", "FAILED")
proc print_status {str status} {
set MAX_STR_LENGTH 70
source .prompt_colors.tcl
puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
}
ips/vivado/scalp_axi4lite/2019.2/lin64/setup.sh 0 → 100755
+ 30
− 0
View file @ aefc3150
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_axi4lite
# Target Device: SCALP xc7z015clg485-2
# Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2020-11-08 07:53:10
#
##################################################################################
# Create aliases
alias create_project='cd .scripts && ./create_prj_scalp_axi4lite.sh && cd ..'
alias clean_project='cd .scripts && ./clean_prj_scalp_axi4lite.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_scalp_axi4lite.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_axi4lite.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_scalp_axi4lite.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_axi4lite.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_scalp_axi4lite.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_scalp_axi4lite.sh && cd ..'
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