Creation of the IP core scalp_axilite and IP packaging for integration in a Zynq SoC.

ips/hw/scalp_axi4lite/component.xml

ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite.vhd

ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_rd_chan.vhd

ips/hw/scalp_axi4lite/src/hdl/scalp_axi4lite_wr_chan.vhd

ips/hw/scalp_axi4lite/src/sim/tb_scalp_axi4lite.vhd

ips/hw/scalp_axi4lite/xgui/scalp_axi4lite_v1_0.tcl

...o/scalp_axi4lite/2019.2/lin64/.scripts/.prompt_colors.tcl

...xi4lite/2019.2/lin64/.scripts/clean_prj_scalp_axi4lite.sh

...i4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.sh

...4lite/2019.2/lin64/.scripts/create_prj_scalp_axi4lite.tcl

...axi4lite/2019.2/lin64/.scripts/open_prj_scalp_axi4lite.sh

ips/vivado/scalp_axi4lite/2019.2/lin64/.scripts/utils.tcl

ips/vivado/scalp_axi4lite/2019.2/lin64/setup.sh