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soma
scalp_firmware
Commits
b20fafb8
Commit
b20fafb8
authored
3 years ago
by
joachim.schmidt
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Update scalp_aurora_phy_rx_fifo
parent
499cb9eb
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ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
+18
-4
18 additions, 4 deletions
...p_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
with
18 additions
and
4 deletions
ips/hw/scalp_aurora_phy_rx_fifo/src/hdl/scalp_aurora_phy_rx_fifo.vhd
+
18
−
4
View file @
b20fafb8
...
...
@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_aurora_phy_rx_fifo
--
-- Last update: 2021-09-
07
-- Last update: 2021-09-
13
--
---------------------------------------------------------------------------------
...
...
@@ -136,9 +136,23 @@ architecture arch of scalp_aurora_phy_rx_fifo is
signal
WestTXM2SLastxS
:
std_ulogic
:
=
'0'
;
-- Attributes
attribute
mark_debug
:
string
;
attribute
keep
:
string
;
attribute
mark_debug
:
string
;
attribute
keep
:
string
;
--
-- attribute mark_debug of WestRXM2SxD : signal is "true";
-- attribute keep of WestRXM2SxD : signal is "true";
-- attribute mark_debug of WestRXS2MxD : signal is "true";
-- attribute keep of WestRXS2MxD : signal is "true";
-- attribute mark_debug of WestTXM2SxD : signal is "true";
-- attribute keep of WestTXM2SxD : signal is "true";
-- attribute mark_debug of WestTXS2MxD : signal is "true";
-- attribute keep of WestTXS2MxD : signal is "true";
-- attribute mark_debug of WestFifoStatusxD : signal is "true";
-- attribute keep of WestFifoStatusxD : signal is "true";
-- attribute mark_debug of WestTXM2SLastxS : signal is "true";
-- attribute keep of WestTXM2SLastxS : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
begin
...
...
@@ -183,7 +197,7 @@ begin
NorthTXM2SLastCtrlxAS
:
NorthTXM2SxD
.
LastxS
<=
'1'
when
(
NorthTXM2SLastxS
=
'1'
)
and
(
NorthTXM2SxD
.
ValidxS
=
'1'
)
else
'0'
;
EastTXM2SLastCtrlxAS
:
EastTXM2SxD
.
LastxS
<=
'1'
when
(
EastTXM2SLastxS
=
'1'
)
and
(
EastTXM2SxD
.
ValidxS
=
'1'
)
else
'0'
;
SouthTXM2SLastCtrlxAS
:
SouthTXM2SxD
.
LastxS
<=
'1'
when
(
SouthTXM2SLastxS
=
'1'
)
and
(
SouthTXM2SxD
.
ValidxS
=
'1'
)
else
'0'
;
WestTXM2SLastCtrlxAS
:
WestTXM2SxD
.
LastxS
<=
'1'
when
(
WestTXM2SLastxS
=
'1'
)
and
(
WestTXM2SxD
.
ValidxS
=
'1'
)
else
'0'
;
WestTXM2SLastCtrlxAS
:
WestTXM2SxD
.
LastxS
<=
'1'
when
(
WestTXM2SLastxS
=
'1'
)
and
(
WestTXM2SxD
.
ValidxS
=
'1'
)
else
'0'
;
elsif
C_CTRL_TLAST
=
false
generate
...
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