Version of the SCALP project created from the vivado_project_creator project...

Version of the SCALP project created from the vivado_project_creator project manager and integrating the Zynq SoC part.

designs/vivado/scalp_firmware/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl

+source "../../../../../../soc/vivado/scalp_zynqps/2019.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file

designs/vivado/scalp_firmware_old/2019.2/src/sim/tb_scalp_firmware.vhd → designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2019.2
 -- Description: Testbench for scalp_firmware
 --
--- Last update: 2020-09-03 11:28:21
+-- Last update: 2020-09-21 13:34:23
 --
 ---------------------------------------------------------------------------------
 

designs/vivado/scalp_firmware_old/2019.2/src/hdl/scalp_zynqps_wrapper.vhd

-----------------------------------------------------------------------------------
---                                 _             _
---                                | |_  ___ _ __(_)__ _
---                                | ' \/ -_) '_ \ / _` |
---                                |_||_\___| .__/_\__,_|
---                                         |_|
---
-----------------------------------------------------------------------------------
---
--- Company: hepia
--- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
---
--- Module Name: scalp_zynqps_wrapper - arch
--- Target Device: SCALP xc7z015clg485-2
--- Tool version: 2019.2
--- Description: scalp_zynqps_wrapper
---
--- Last update: 2020-09-07
---
----------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity scalp_zynqps_wrapper is
-
-    port (
-        -- Processor interface
-        FIXED_IO_ps_clk     : inout std_logic;
-        FIXED_IO_ps_porb    : inout std_logic;
-        FIXED_IO_ps_srstb   : inout std_logic;
-        FclkClk0xCO         : out   std_logic;
-        FclkReset0xRO       : out   std_logic;
-        -- DDR interface
-        DDR_addr            : inout std_logic_vector (14 downto 0);
-        DDR_ba              : inout std_logic_vector (2 downto 0);
-        DDR_cas_n           : inout std_logic;
-        DDR_ck_n            : inout std_logic;
-        DDR_ck_p            : inout std_logic;
-        DDR_cke             : inout std_logic;
-        DDR_cs_n            : inout std_logic;
-        DDR_dm              : inout std_logic_vector (3 downto 0);
-        DDR_dq              : inout std_logic_vector (31 downto 0);
-        DDR_dqs_n           : inout std_logic_vector (3 downto 0);
-        DDR_dqs_p           : inout std_logic_vector (3 downto 0);
-        DDR_odt             : inout std_logic;
-        DDR_ras_n           : inout std_logic;
-        DDR_reset_n         : inout std_logic;
-        DDR_we_n            : inout std_logic;
-        FIXED_IO_ddr_vrn    : inout std_logic;
-        FIXED_IO_ddr_vrp    : inout std_logic;
-        -- USB interface
-        Usb0VBusPwrFaultxSI : in    std_logic;
-        -- SPI1 used as uWire master. Clk, Data and LE signals are outputs
-        -- SPI1 inputs are unused. Clk is connected to SCLK, Data to MOSI and LE to SS
-        Spi1MOSIxSO         : out   std_logic;
-        Spi1SSxSO           : out   std_logic;
-        Spi1SclkxCO         : out   std_logic;
-        -- MIO
-        FIXED_IO_mio        : inout std_logic_vector (53 downto 0));
-
-end scalp_zynqps_wrapper;
-
-architecture arch of scalp_zynqps_wrapper is
-
-begin
-
-    ScalpZynqPSxI : entity work.scalp_zynqps
-        port map (
-            DDR_addr            => DDR_addr,
-            DDR_ba              => DDR_ba,
-            DDR_cas_n           => DDR_cas_n,
-            DDR_ck_n            => DDR_ck_n,
-            DDR_ck_p            => DDR_ck_p,
-            DDR_cke             => DDR_cke,
-            DDR_cs_n            => DDR_cs_n,
-            DDR_dm              => DDR_dm,
-            DDR_dq              => DDR_dq,
-            DDR_dqs_n           => DDR_dqs_n,
-            DDR_dqs_p           => DDR_dqs_p,
-            DDR_odt             => DDR_odt,
-            DDR_ras_n           => DDR_ras_n,
-            DDR_reset_n         => DDR_reset_n,
-            DDR_we_n            => DDR_we_n,
-            FIXED_IO_ddr_vrn    => FIXED_IO_ddr_vrn,
-            FIXED_IO_ddr_vrp    => FIXED_IO_ddr_vrp,
-            FIXED_IO_mio        => FIXED_IO_mio,
-            FIXED_IO_ps_clk     => FIXED_IO_ps_clk,
-            FIXED_IO_ps_porb    => FIXED_IO_ps_porb,
-            FIXED_IO_ps_srstb   => FIXED_IO_ps_srstb,
-            FclkClk0xCO         => FclkClk0xCO,
-            FclkReset0xRO(0)    => FclkReset0xRO,
-            Spi1MOSIxSO         => Spi1MOSIxSO,
-            Spi1SSxSO           => Spi1SSxSO,
-            Spi1SclkxCO         => Spi1SclkxCO,
-            Usb0VBusPwrFaultxSI => Usb0VBusPwrFaultxSI);
-
-end arch;

designs/vivado/scalp_firmware_old/2019.2/src/ipi_tcl/scalp_firmware_ipi.tcl

-set PRJ_ZYNQPS "scalp_zynqps"
-set VIVADO_VERSION "2019.2"
-
-set zynqps_dir "../../../../../../soc/vivado/${PRJ_ZYNQPS}/${VIVADO_VERSION}/src/ipi_tcl"
-set zynqps_ipi "${PRJ_ZYNQPS}_ipi.tcl"
-
-source "${zynqps_dir}/${zynqps_ipi}"

tools/config/scalp_firmware.json

@@ -28,7 +28,7 @@
             "axi4_pkg"          : "enable"
         },
         "soc" : {
-            "scalp_zynqps" : "true"
+            "scalp_zynqps" : "enable"
         }
     }
 }