Move simulation HDL into different sub-dirs

hog-build-info/hog-build-info.srcs/sim_1/new/tb_hog_build_info_regs.vhd → hog-build-info/hog-build-info.srcs/sim/registers_bank_tb/tb_hog_build_info_regs.vhd

@@ -5,7 +5,7 @@
 -- Create Date: 03/13/2025 01:17:53 PM
 -- Design Name: Test bench Hog build info registers bank
 -- Module Name: tb_hog_build_info_regs - Behavioral
--- Project Name: 
+-- Project Name: Hog build info
 -- Target Devices: 
 -- Tool Versions: 
 -- Description: Test bench for the Hog build info register bank
@@ -33,7 +33,7 @@ architecture Behavioral of tb_hog_build_info_regs is
   --- Hog build info register bank
   component hog_build_info_regs is
     generic (
-      C_ADDR_WIDTH: integer := 32   -- Width of the addresses
+      C_ADDR_WIDTH: integer := 4   -- Width of the addresses
       );
     
     port (
@@ -50,7 +50,7 @@ architecture Behavioral of tb_hog_build_info_regs is
       Hog_global_ver_i  : in std_logic_vector(31 downto 0); -- Hog build global version
       hog_global_sha_i  : in std_logic_vector(31 downto 0) -- Hog build global latest commit SHA
       );
-  end component;
+  end component hog_build_info_regs;
 
   -- Clock signal and period
   constant CLK_PERIOD : time := 10 ns;
@@ -60,14 +60,14 @@ architecture Behavioral of tb_hog_build_info_regs is
   signal resetn_s : std_logic := '1';
 
   -- Config
-  constant C_ADDR_WIDTH: integer := 32;
+  constant C_ADDR_WIDTH: integer := 4;
 
   -- Registers addresses
   constant GDR_BASEADDR : integer := 0; -- Global date register
   constant GTR_BASEADDR : integer := 4; -- Global time register
   constant GVR_BASEADDR : integer := 8; -- Global version register
   constant GSR_BASEADDR : integer := 12; -- Global SHA register
-  constant UNK_BASEADDR : integer := 100; -- Unknown register
+  constant UNK_BASEADDR : integer := 14; -- Unknown register
 
   -- Fake Hog build info
   constant hog_global_date : std_logic_vector(31 downto 0) := X"13032025";
@@ -91,12 +91,12 @@ architecture Behavioral of tb_hog_build_info_regs is
   signal hog_global_sha_s  : std_logic_vector(31 downto 0) := (others => '0');
 
   -- Test bench steps
-  signal reset_done_s: std_logic := '0';
-  signal check_reg_0_data_s: std_logic := '0';
-  signal check_reg_1_data_s: std_logic := '0';
-  signal check_reg_2_data_s: std_logic := '0';
-  signal check_reg_3_data_s: std_logic := '0';
-  signal check_reg_unk_data_s: std_logic := '0';
+  signal reset_done_s         : std_logic := '0';
+  signal check_reg_0_data_s   : std_logic := '0';
+  signal check_reg_1_data_s   : std_logic := '0';
+  signal check_reg_2_data_s   : std_logic := '0';
+  signal check_reg_3_data_s   : std_logic := '0';
+  signal check_reg_unk_data_s : std_logic := '0';
 
   procedure request_access_to_reg(
     constant reg_addr : in integer;