Create the top level entity for the new register

Top/hog-build-info/list/xil_defaultlib.src

+hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg.vhd top=hog_build_info_reg 93

hog-build-info/hog-build-info.srcs/sources_1/new/hog_build_info_reg.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 03/10/2025 06:56:35 AM
+-- Design Name: 
+-- Module Name: hog_build_info_reg - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hog_build_info_reg is
+  Generic (
+    -- Global Generic Variables
+    GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_VER  : std_logic_vector(31 downto 0) := (others => '0');
+    GLOBAL_SHA  : std_logic_vector(31 downto 0) := (others => '0')
+    );
+--  Port ( );
+end hog_build_info_reg;
+
+architecture Behavioral of hog_build_info_reg is
+
+begin
+
+
+end Behavioral;