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Commit f8b97d0b authored by sebastie.gendre's avatar sebastie.gendre
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Write a small simulation to print Hog build info

parent bc6a1c1e
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......@@ -21,23 +21,25 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use ieee.numeric_std.all;
use std.textio.all;
entity explore_build_info is
-- Port ( );
Generic (
-- Global Generic Variables
GLOBAL_DATE : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_TIME : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_VER : std_logic_vector(31 downto 0) := (others => '0');
GLOBAL_SHA : std_logic_vector(31 downto 0) := (others => '0')
);
end explore_build_info;
architecture Behavioral of explore_build_info is
begin
assert false
report "GLOBAL_DATE: " & to_hstring(to_bitvector(GLOBAL_DATE))
severity note;
end Behavioral;
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