Fix how Labo1B is managed by git

Labo1B @ 06239fba

-Subproject commit 06239fba87b170a7edcc937920d5a4016df2ec00

Labo1B/README.md

+# Fichiers du labo 1B #
+

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.v

+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Thu Nov 28 16:27:01 2024
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.v
+// Design      : design_1_clk_wiz_0_1
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire clk_out1;
+  wire locked;
+  wire reset;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .clk_out1(clk_out1),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_design_1_clk_wiz_0_1;
+  wire clk_out1;
+  wire clk_out1_design_1_clk_wiz_0_1;
+  wire clkfbout_buf_design_1_clk_wiz_0_1;
+  wire clkfbout_design_1_clk_wiz_0_1;
+  wire locked;
+  wire reset;
+  wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_design_1_clk_wiz_0_1),
+        .O(clkfbout_buf_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_out1_design_1_clk_wiz_0_1),
+        .O(clk_out1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(12),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(10.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(3),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1),
+        .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1),
+        .CLKIN1(clk_in1_design_1_clk_wiz_0_1),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(clk_out1_design_1_clk_wiz_0_1),
+        .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+        .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_sim_netlist.vhdl

+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Thu Nov 28 16:27:01 2024
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.vhdl
+-- Design      : design_1_clk_wiz_0_1
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_design_1_clk_wiz_0_1,
+      O => clkfbout_buf_design_1_clk_wiz_0_1
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_design_1_clk_wiz_0_1
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_out1_design_1_clk_wiz_0_1,
+      O => clk_out1
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 12,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 10.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 3,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 1,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 1,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1,
+      CLKFBOUT => clkfbout_design_1_clk_wiz_0_1,
+      CLKIN1 => clk_in1_design_1_clk_wiz_0_1,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => clk_out1_design_1_clk_wiz_0_1,
+      CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+      CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      clk_out1 => clk_out1,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.v

+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Thu Nov 28 16:27:01 2024
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.v
+// Design      : design_1_clk_wiz_0_1
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+  output clk_out1 /* synthesis syn_isclock = 1 */;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/9/a9ad1272a4ff99ca/design_1_clk_wiz_0_1_stub.vhdl

+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Thu Nov 28 16:27:01 2024
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.vhdl
+-- Design      : design_1_clk_wiz_0_1
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.v

+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Thu Nov 28 16:19:53 2024
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.v
+// Design      : design_1_clk_wiz_0_1
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire clk_out1;
+  wire locked;
+  wire reset;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .clk_out1(clk_out1),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_design_1_clk_wiz_0_1;
+  wire clk_out1;
+  wire clk_out1_design_1_clk_wiz_0_1;
+  wire clkfbout_buf_design_1_clk_wiz_0_1;
+  wire clkfbout_design_1_clk_wiz_0_1;
+  wire locked;
+  wire reset;
+  wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_design_1_clk_wiz_0_1),
+        .O(clkfbout_buf_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_out1_design_1_clk_wiz_0_1),
+        .O(clk_out1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(12),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(10.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(3),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1),
+        .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1),
+        .CLKIN1(clk_in1_design_1_clk_wiz_0_1),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(clk_out1_design_1_clk_wiz_0_1),
+        .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+        .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_sim_netlist.vhdl

+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Thu Nov 28 16:19:53 2024
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.vhdl
+-- Design      : design_1_clk_wiz_0_1
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_design_1_clk_wiz_0_1,
+      O => clkfbout_buf_design_1_clk_wiz_0_1
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_design_1_clk_wiz_0_1
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_out1_design_1_clk_wiz_0_1,
+      O => clk_out1
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 12,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 10.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 3,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 1,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 1,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1,
+      CLKFBOUT => clkfbout_design_1_clk_wiz_0_1,
+      CLKIN1 => clk_in1_design_1_clk_wiz_0_1,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => clk_out1_design_1_clk_wiz_0_1,
+      CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+      CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      clk_out1 => clk_out1,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.v

+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+// Date        : Thu Nov 28 16:19:53 2024
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.v
+// Design      : design_1_clk_wiz_0_1
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a200tsbg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+  output clk_out1 /* synthesis syn_isclock = 1 */;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/design_1_clk_wiz_0_1_stub.vhdl

+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1.2 (lin64) Build 5164865 Thu Sep  5 14:36:28 MDT 2024
+-- Date        : Thu Nov 28 16:19:53 2024
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_stub.vhdl
+-- Design      : design_1_clk_wiz_0_1
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a200tsbg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1.2/a/d/adff1593d44ebeb2/stats.txt

+NumberHits:1
+Timestamp: Thu Nov 28 15:23:35 UTC 2024

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1/8/0/80fb27f1c7ed18c7/design_1_clk_wiz_0_1_sim_netlist.v

+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+// Date        : Thu Nov 14 05:07:21 2024
+// Host        : hogtest running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.v
+// Design      : design_1_clk_wiz_0_1
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7z010iclg225-1L
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire clk_out1;
+  wire locked;
+  wire reset;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .clk_out1(clk_out1),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_design_1_clk_wiz_0_1;
+  wire clk_out1;
+  wire clk_out1_design_1_clk_wiz_0_1;
+  wire clkfbout_buf_design_1_clk_wiz_0_1;
+  wire clkfbout_design_1_clk_wiz_0_1;
+  wire locked;
+  wire reset;
+  wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_design_1_clk_wiz_0_1),
+        .O(clkfbout_buf_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_design_1_clk_wiz_0_1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_out1_design_1_clk_wiz_0_1),
+        .O(clk_out1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(12),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(10.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(3),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_design_1_clk_wiz_0_1),
+        .CLKFBOUT(clkfbout_design_1_clk_wiz_0_1),
+        .CLKIN1(clk_in1_design_1_clk_wiz_0_1),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(clk_out1_design_1_clk_wiz_0_1),
+        .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+        .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

Labo1B/Vivado/labo1b/labo1b.cache/ip/2024.1/8/0/80fb27f1c7ed18c7/design_1_clk_wiz_0_1_sim_netlist.vhdl

+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2024.1 (lin64) Build 5076996 Wed May 22 18:36:09 MDT 2024
+-- Date        : Thu Nov 14 05:07:21 2024
+-- Host        : hogtest running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_clk_wiz_0_1_sim_netlist.vhdl
+-- Design      : design_1_clk_wiz_0_1
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7z010iclg225-1L
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz is
+  signal clk_in1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clk_out1_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_buf_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal clkfbout_design_1_clk_wiz_0_1 : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_design_1_clk_wiz_0_1,
+      O => clkfbout_buf_design_1_clk_wiz_0_1
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_design_1_clk_wiz_0_1
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_out1_design_1_clk_wiz_0_1,
+      O => clk_out1
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 12,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 10.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 3,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 1,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 1,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_design_1_clk_wiz_0_1,
+      CLKFBOUT => clkfbout_design_1_clk_wiz_0_1,
+      CLKIN1 => clk_in1_design_1_clk_wiz_0_1,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => clk_out1_design_1_clk_wiz_0_1,
+      CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+      CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_design_1_clk_wiz_0_1_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      clk_out1 => clk_out1,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;