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Commit da3cce6f authored by Boris Stefanovic's avatar Boris Stefanovic
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ADD: report

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...@@ -53,4 +53,23 @@ a.out ...@@ -53,4 +53,23 @@ a.out
meta/circ/*.png meta/circ/*.png
meta/graphics/*.pdf meta/graphics/*.pdf
meta/report/**/*.aux
meta/report/**/*.lof
meta/report/**/*.log
meta/report/**/*.lot
meta/report/**/*.out
meta/report/**/*.pdf
meta/report/**/*.ptc
meta/report/**/*.synctex.gz
meta/report/**/*.synctex(busy)
meta/report/**/*.tex.swp
meta/report/**/*.bbl
meta/report/**/*.bcf
meta/report/**/*.blg
meta/report/**/*.run.xml
meta/report/**/*.dvi
meta/report/xout/
meta/report/*.pdf meta/report/*.pdf
!meta/report/template/images/statements/originalstatements.pdf
SRCD := hw/spinal/kyber SRCD := hw/spinal/kyber
REPORT := ISC_EMB_memoire_diplome_Stefanovic_Upegui_2024.pdf
LATEX_MAIN_NAME := toplevel
LATEX_MAIN_FILE := ${LATEX_MAIN_NAME}.tex
LATEX_MAIN_OUTPUT := ${LATEX_MAIN_NAME}.pdf
LATEX_TMP_DIR := /tmp/latex-$(shell date +%Y%m%d-%H%M%S-%N)
#LATEX_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${LATEX_TMP_DIR} --aux-directory=${LATEX_TMP_DIR} ${LATEX_MAIN_FILE}
LATEX_CMD_PDF := pdflatex -interaction=nonstopmode -synctex=1 --output-directory=${LATEX_TMP_DIR} ${LATEX_MAIN_FILE}
LATEX_CMD_BIB := biber --input-directory ${LATEX_TMP_DIR} --output-directory ${LATEX_TMP_DIR} ${LATEX_MAIN_NAME}
LATEX_SRC := $(shell find meta/report -type f -name '*.tex')
ntt: clean $(wildcard ${SRCD}/ntt/*) ntt: clean $(wildcard ${SRCD}/ntt/*)
sbt "runMain kyber.ntt.NttGEN"
sbt "runMain kyber.ntt.NttSIM" sbt "runMain kyber.ntt.NttSIM"
ntt-gen: clean $(wildcard ${SRCD}/ntt/*)
sbt "runMain kyber.ntt.NttGEN" sbt "runMain kyber.ntt.NttGEN"
ntt-sim: clean $(wildcard ${SRCD}/ntt/*)
sbt "runMain kyber.ntt.NttSIM"
pdf: ${LATEX_SRC}
mkdir -p ${LATEX_TMP_DIR}
cd meta/report && \
${LATEX_CMD_PDF} && \
${LATEX_CMD_PDF} && \
${LATEX_CMD_PDF} && \
${LATEX_CMD_BIB} && \
${LATEX_CMD_PDF} && \
${LATEX_CMD_PDF} && \
cp ${LATEX_TMP_DIR}/${LATEX_MAIN_OUTPUT} ${REPORT}
rm -rf ${LATEX_TMP_DIR}
view: pdf
#firefox meta/report/${LATEX_MAIN_OUTPUT}
firefox meta/report/${REPORT}
repdf: clean pdf
review: clean view
clean: clean:
rm -rf gen simWorkspace target rm -rf gen out simWorkspace target meta/report/xout meta/report/*.pdf
find meta/report -type f \
\(\
-name '*.aux' -o \
-name '*.lof' -o \
-name '*.log' -o \
-name '*.lot' -o \
-name '*.out' -o \
-name '*.ptc' -o \
-name '*.synctex.gz' -o \
-name '*.bbl' -o \
-name '*.bcf' -o \
-name '*.blg' -o \
-name '*.run.xml' -o \
-name '*.dvi' -o \
-name '*.pdf' \
-not -name 'originalstatements.pdf' \
\)\
-print -delete
.PHONY: clean ntt pdf repdf review view
.PHONY: clean ntt .NOTPARALLEL: repdf review
/*package kyber
import kyber.ntt.NumberTheoreticTransformSequential
import spinal.core._
case class TopLevel() extends Component {
val io = new Bundle {
val ntt_addr = in UInt (8 bits)
val ntt_data_i = in SInt (16 bits)
val ntt_load = in Bool()
val ntt_start = in Bool()
val ntt_interrupt = in Bool()
val ntt_data_o = out SInt (16 bits)
val ntt_ready = out Bool()
val ntt_valid = out Bool()
}
val ntt = NumberTheoreticTransformSequential()
io.ntt_addr <> ntt.io.addr
io.ntt_data_i <> ntt.io.data_i
io.ntt_load <> ntt.io.load
io.ntt_start <> ntt.io.start
io.ntt_interrupt <> ntt.io.interrupt
io.ntt_data_o <> ntt.io.data_o
io.ntt_ready <> ntt.io.ready
io.ntt_valid <> ntt.io.valid
}
object TopLevelVhdl extends App {
Config.spinal.generateVhdl(TopLevel())
}*/
/*package kyber
import spinal.core._
import spinal.core.formal._
// You need SymbiYosys to be installed.
// See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
object TopLevelFml extends App {
FormalConfig.withBMC(10).doVerify(new Component {
val dut = FormalDut(TopLevel())
// Ensure the formal test start with a reset
assumeInitial(clockDomain.isResetActive)
// Provide some stimulus
anyseq(dut.io.ntt_addr)
anyseq(dut.io.ntt_data_i)
anyseq(dut.io.ntt_load)
// Check the state initial value and increment
//assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0))
})
}*/
/*package kyber
import spinal.core._
import spinal.core.sim._
object TopLevelSim extends App {
Config.sim.compile(TopLevel()).doSim { dut =>
// Fork a process to generate the reset and the clock on the dut
dut.clockDomain.forkStimulus(period = 10)
var modelState = 0
for (idx <- 0 to 99) {
// Drive the dut inputs with random values
dut.io.ntt_addr.randomize()
dut.io.ntt_data_i.randomize()
// Wait a rising edge on the clock
dut.clockDomain.waitRisingEdge()
// Check that the dut values match with the reference model ones
//val modelFlag = modelState == 0 || dut.io.cond1.toBoolean
//assert(dut.io.state.toInt == modelState)
//assert(dut.io.flag.toBoolean == modelFlag)
// Update the reference model value
//if (dut.io.cond0.toBoolean) {
// modelState = (modelState + 1) & 0xff
//}
}
}
}*/
...@@ -7,6 +7,8 @@ import spinal.core._ ...@@ -7,6 +7,8 @@ import spinal.core._
import spinal.core.sim._ import spinal.core.sim._
import spinal.lib.fsm._ import spinal.lib.fsm._
import java.io.File
/** /**
* Performs a <b>Number Theoretic Transform</b>, * Performs a <b>Number Theoretic Transform</b>,
...@@ -120,8 +122,14 @@ case class Ntt(nports: Int = 1) extends Component { ...@@ -120,8 +122,14 @@ case class Ntt(nports: Int = 1) extends Component {
object NttGEN extends App { object NttGEN extends App {
val report = Config.spinal.generateVhdl(Ntt(nports = 128)) val dir = Config.spinal.targetDirectory
val plain = "Ntt.vhd"
for (i <- 0 to 7) {
val nports = 1 << i
val report = Config.spinal.generateVhdl(Ntt(nports = nports))
report.printPruned() report.printPruned()
new File(dir + "/" + plain).renameTo(new File(dir + "/Ntt_%03d.vhd".format(nports)))
}
} }
......
...@@ -34,6 +34,42 @@ case class NttAxi(nports: Int = 1) extends Component { ...@@ -34,6 +34,42 @@ case class NttAxi(nports: Int = 1) extends Component {
useStrb = false, useStrb = false,
))) )))
} }
val ntt = Ntt(nports = nports)
// SPEC (AXI4) : on reset, drive VALID to '0'
val reg_rvalid = Reg(Bool()) init false
reg_rvalid := ntt.io.o_valid
val reg_bvalid = Reg(Bool()) init false
reg_bvalid := True
val sig_is_write = Bool() // TODO: define
// NTT INPUTS
ntt.io.i_data := io.axi.w.data(ntt.io.i_data.getBitsWidth - 1 downto 0)
ntt.io.i_addr := sig_is_write.mux(
io.axi.aw.addr.asBits.asUInt(ntt.io.i_addr.getBitsWidth - 1 downto 0),
io.axi.ar.addr.asBits.asUInt(ntt.io.i_addr.getBitsWidth - 1 downto 0),
)
ntt.io.i_load
ntt.io.i_go
ntt.io.i_stop
// CONSUMABLE
io.axi.ar.addr
io.axi.ar.valid
io.axi.r.ready
io.axi.aw.addr
io.axi.aw.valid
io.axi.w.data
io.axi.w.valid
// SETTABLE
io.axi.ar.ready := True
io.axi.r.data := ((ntt.io.o_data.getBitsWidth - 1 downto 0) -> ntt.io.o_data, default -> false)
io.axi.r.valid := ntt.io.o_valid
io.axi.aw.ready := True
io.axi.w.ready := ntt.io.o_ready
} }
......
package kyber.poly
import spinal.core._
case class PolyBundle() extends Bundle {
val coeffs = Vec.fill(256)(SInt(16 bits))
}
package kyber.poly
import spinal.core._
case class PolyCompress(compressedBytesLen: Int) extends Component {
require(compressedBytesLen == 128 || compressedBytesLen == 160)
val io = new Bundle {
val poly = in(PolyBundle())
}
}
package kyber.verify
import spinal.core._
case class Verify()extends Component{
val io=new Bundle{}
}
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ntt is
port (
i_addr: in std_logic_vector(7 downto 0);
i_data: in std_logic_vector(15 downto 0);
i_load: in std_logic;
i_start: in std_logic;
i_interrupt: in std_logic;
o_data: out std_logic_vector(15 downto 0);
o_ready: out std_logic;
o_valid: out std_logic;
reset: in std_logic;
clk: in std_logic
);
end ntt;
architecture arch of ntt is
type t_zetas is array(0 to 127) of signed(15 downto 0);
constant c_zetas: t_zetas := (
-1044, -758, -359, -1517, 1493, 1422, 287, 202, -171, 622, 1577, 182, 962, -1202, -1474, 1468,
573, -1325, 264, 383, -829, 1458, -1602, -130, -681, 1017, 732, 608, -1542, 411, -205, -1571,
1223, 652, -552, 1015, -1293, 1491, -282, -1544, 516, -8, -320, -666, -1618, -1162, 126, 1469,
-853, -90, -271, 830, 107, -1421, -247, -951, -398, 961, -1508, -725, 448, -1065, 677, -1275,
-1103, 430, 555, 843, -1251, 871, 1550, 105, 422, 587, 177, -235, -291, -460, 1574, 1653,
-246, 778, 1159, -147, -777, 1483, -602, 1119, -1590, 644, -872, 349, 418, 329, -156, -75,
817, 1097, 603, 610, 1322, -1285, -1465, 384, -1215, -136, 1218, -1335, -874, 220, -1187, -1659,
-1185, -1530, -1278, 794, -1510, -854, -870, 478, -108, -308, 996, 991, 958, -1460, 1522, 1628
);
begin
end arch;
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="3.8.0" version="1.0">
This file is intended to be loaded by Logisim-evolution v3.8.0(https://github.com/logisim-evolution/).
<lib desc="#Wiring" name="0">
<tool name="Pin">
<a name="appearance" val="classic"/>
</tool>
</lib>
<lib desc="#Gates" name="1"/>
<lib desc="#Plexers" name="2"/>
<lib desc="#Arithmetic" name="3"/>
<lib desc="#Memory" name="4"/>
<lib desc="#I/O" name="5"/>
<lib desc="#TTL" name="6"/>
<lib desc="#TCL" name="7"/>
<lib desc="#Base" name="8"/>
<lib desc="#BFH-Praktika" name="9"/>
<lib desc="#Input/Output-Extra" name="10"/>
<lib desc="#Soc" name="11"/>
<main name="main"/>
<options>
<a name="gateUndefined" val="ignore"/>
<a name="simlimit" val="1000"/>
<a name="simrand" val="0"/>
</options>
<mappings>
<tool lib="8" map="Button2" name="Poke Tool"/>
<tool lib="8" map="Button3" name="Menu Tool"/>
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
</mappings>
<toolbar>
<tool lib="8" name="Poke Tool"/>
<tool lib="8" name="Edit Tool"/>
<tool lib="8" name="Wiring Tool"/>
<tool lib="8" name="Text Tool"/>
<sep/>
<tool lib="0" name="Pin"/>
<tool lib="0" name="Pin">
<a name="facing" val="west"/>
<a name="output" val="true"/>
</tool>
<sep/>
<tool lib="1" name="NOT Gate"/>
<tool lib="1" name="AND Gate"/>
<tool lib="1" name="OR Gate"/>
<tool lib="1" name="XOR Gate"/>
<tool lib="1" name="NAND Gate"/>
<tool lib="1" name="NOR Gate"/>
<sep/>
<tool lib="4" name="D Flip-Flop"/>
<tool lib="4" name="Register"/>
</toolbar>
<circuit name="main">
<a name="appearance" val="logisim_evolution"/>
<a name="circuit" val="main"/>
<a name="circuitnamedboxfixedsize" val="true"/>
<a name="simulationFrequency" val="1.0"/>
<comp lib="0" loc="(160,240)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="EN"/>
</comp>
<comp lib="0" loc="(160,280)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="ZERO"/>
</comp>
<comp lib="0" loc="(160,340)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="label" val="CLK"/>
</comp>
<comp lib="0" loc="(460,230)" name="Constant">
<a name="value" val="0x0"/>
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(540,240)" name="Constant"/>
<comp lib="0" loc="(550,120)" name="Constant">
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(570,280)" name="Constant">
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(660,400)" name="Constant">
<a name="value" val="0x6"/>
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(660,530)" name="Constant"/>
<comp lib="0" loc="(690,570)" name="Constant">
<a name="value" val="0x0"/>
</comp>
<comp lib="0" loc="(860,220)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="VALUE"/>
<a name="output" val="true"/>
<a name="width" val="3"/>
</comp>
<comp lib="0" loc="(860,390)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="FULL"/>
<a name="output" val="true"/>
</comp>
<comp lib="0" loc="(860,510)" name="Pin">
<a name="appearance" val="NewPins"/>
<a name="facing" val="west"/>
<a name="label" val="OVERFLOW"/>
<a name="output" val="true"/>
</comp>
<comp lib="1" loc="(580,510)" name="AND Gate">
<a name="inputs" val="3"/>
<a name="negate2" val="true"/>
</comp>
<comp lib="2" loc="(430,210)" name="Multiplexer">
<a name="width" val="3"/>
</comp>
<comp lib="2" loc="(500,220)" name="Multiplexer">
<a name="width" val="3"/>
</comp>
<comp lib="3" loc="(600,130)" name="Adder">
<a name="width" val="3"/>
</comp>
<comp lib="3" loc="(720,390)" name="Comparator">
<a name="mode" val="unsigned"/>
<a name="width" val="3"/>
</comp>
<comp lib="4" loc="(540,190)" name="Register">
<a name="appearance" val="logisim_evolution"/>
<a name="width" val="3"/>
</comp>
<comp lib="4" loc="(660,480)" name="Register">
<a name="appearance" val="logisim_evolution"/>
<a name="width" val="1"/>
</comp>
<comp lib="8" loc="(580,431)" name="Text">
<a name="font" val="Monospaced bold 16"/>
<a name="text" val="combinations = 7 = (6+1)"/>
</comp>
<wire from="(160,240)" to="(360,240)"/>
<wire from="(160,280)" to="(320,280)"/>
<wire from="(160,340)" to="(240,340)"/>
<wire from="(240,340)" to="(240,550)"/>
<wire from="(240,340)" to="(540,340)"/>
<wire from="(240,550)" to="(660,550)"/>
<wire from="(320,280)" to="(320,530)"/>
<wire from="(320,280)" to="(480,280)"/>
<wire from="(320,530)" to="(520,530)"/>
<wire from="(360,220)" to="(400,220)"/>
<wire from="(360,240)" to="(360,510)"/>
<wire from="(360,240)" to="(410,240)"/>
<wire from="(360,510)" to="(530,510)"/>
<wire from="(360,90)" to="(360,220)"/>
<wire from="(360,90)" to="(620,90)"/>
<wire from="(380,180)" to="(380,200)"/>
<wire from="(380,180)" to="(540,180)"/>
<wire from="(380,200)" to="(400,200)"/>
<wire from="(410,230)" to="(410,240)"/>
<wire from="(430,210)" to="(470,210)"/>
<wire from="(460,230)" to="(470,230)"/>
<wire from="(480,240)" to="(480,280)"/>
<wire from="(500,220)" to="(540,220)"/>
<wire from="(510,470)" to="(510,490)"/>
<wire from="(510,470)" to="(740,470)"/>
<wire from="(510,490)" to="(530,490)"/>
<wire from="(540,140)" to="(540,180)"/>
<wire from="(540,140)" to="(560,140)"/>
<wire from="(540,180)" to="(660,180)"/>
<wire from="(540,260)" to="(540,340)"/>
<wire from="(550,120)" to="(560,120)"/>
<wire from="(580,510)" to="(660,510)"/>
<wire from="(600,130)" to="(620,130)"/>
<wire from="(600,220)" to="(660,220)"/>
<wire from="(620,90)" to="(620,130)"/>
<wire from="(660,180)" to="(660,220)"/>
<wire from="(660,220)" to="(660,380)"/>
<wire from="(660,220)" to="(860,220)"/>
<wire from="(660,380)" to="(680,380)"/>
<wire from="(660,400)" to="(680,400)"/>
<wire from="(720,390)" to="(740,390)"/>
<wire from="(720,510)" to="(860,510)"/>
<wire from="(740,390)" to="(740,470)"/>
<wire from="(740,390)" to="(860,390)"/>
</circuit>
</project>
No preview for this file type
title: Lattice Based Post-Quantum Cryptographic Components on FPGA - Towards an ASIC Implementation of the Kyber Key Encapsulation Algorithm
author: Boris Stefanovic
date: 2024-05-27
$$\null\hfill Right justify$$
# Acknowledgements
As this is work dealing with key exchange algorithms, it seems fitting to begin by appreciating my time spent with all the people who foster trust in a time of contempt.
I would like to express my gratitude to Marc for his time and help with making sense of obscure proof-of-concept VHDL code found on shady GitHub repositories. Fun as it was, remind me not to do that again for a full week. Thank you for helping me through this and other well-chosen tricky situations.
Then, to Big Léo, for always helping me keep my head when the scent of cloves rises. Thank you for your trust and friendship.
Last but not least, Alessia, for always doing your best to heal a world that still lacks the ability to do so on its own, steadily, one step at a time. Thank you for being such an inspiration!
# Abstract
# List of Acronyms
- ASIC : Application Specific Integrated Circuit
- CLB : Configurable Logic Block
- FPGA : Field Programmable Gate Array
- IP : Intellectual Property
- LUT : LookUp Table
- LWE : Learning With Errors
- NIST : National Institute of Standards and Technology
- PQC : Post-Quantum Cryptography
- RTL : Register Transfer Level
- SVP : Shortest Vector Problem
- TCL : Tool Command Language
- VHDL : V(ery High Speed Integrated Circuit) Hardware Description Language
# List of Illustrations
# List of URLs
# List of Appendices
# Introduction
NIST
\ No newline at end of file
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