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Commit 997921ee authored by joachim.schmidt's avatar joachim.schmidt
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Updated firmware design "scalp_firmware" with back pressure management for each receiving fifo.

parent 2b34341c
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designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Cleanup project directory # Description: Cleanup project directory
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware' # Description: TCL script for re-creating Vivado project 'scalp_firmware'
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
...@@ -65,15 +65,21 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -65,15 +65,21 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC) # add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
set_property is_enabled true [get_files $src_dir/constrs/debug.xdc] set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc] set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc] set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc] set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
#add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
# add IPs source file # add IPs source file
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd] set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list { foreach j $vhdl_ips_file_list {
...@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
...@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list { ...@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list {
print_status "VHDL 2008 mode configured for testbench sources" "OK" print_status "VHDL 2008 mode configured for testbench sources" "OK"
# Add packages sources # Add packages sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list add_files -norecurse $vhdl_pkg_file_list
foreach j $vhdl_pkg_file_list { foreach j $vhdl_pkg_file_list {
...@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
}
print_status "Add packages sources" "OK" print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK" print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files # Add SoC wrapper sources files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd] set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list { foreach j $vhdl_soc_file_list {
...@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { ...@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
} }
}
print_status "Add SoC wrapper sources" "OK" print_status "Add SoC wrapper sources" "OK"
print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK" print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Export the hardware design to SDK # Description: Export the hardware design to SDK
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate bitstream file # Description: Generate bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate bitstream file # Description: TCL script used to generate bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Generate software application # Description: Generate software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to generate software application # Description: TCL script used to generate software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load bitstream file # Description: Load bitstream file
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load FPGA bitstream # Description: TCL script used to load FPGA bitstream
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Load software application # Description: Load software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script used to load software application # Description: TCL script used to load software application
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
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...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: Project management utilities # Description: Project management utilities
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2019.2 # Tool version: 2019.2
# Description: TCL script creating aliases for Vivado project management scripts # Description: TCL script creating aliases for Vivado project management scripts
# #
# Last update: 2020-10-13 13:10:02 # Last update: 2020-11-07 09:14:14
# #
################################################################################## ##################################################################################
......
designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
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...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2019.2 -- Tool version: 2019.2
-- Description: scalp_firmware -- Description: scalp_firmware
-- --
-- Last update: 2020-10-13 -- Last update: 2020-11-07
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -316,6 +316,18 @@ architecture arch of scalp_firmware is ...@@ -316,6 +316,18 @@ architecture arch of scalp_firmware is
WestRXUFCM2SxDO : out t_axi4ufcm2s_rx; WestRXUFCM2SxDO : out t_axi4ufcm2s_rx;
WestTXUFCM2SxDI : in t_axi4ufcm2s_tx; WestTXUFCM2SxDI : in t_axi4ufcm2s_tx;
WestTXUFCS2MxDO : out t_axi4ufcs2m_tx; WestTXUFCS2MxDO : out t_axi4ufcs2m_tx;
NorthRXNFCM2SxDO : out t_axi4nfcm2s;
NorthTXNFCM2SxDI : in t_axi4nfcm2s;
NorthTXNFCS2MxDO : out t_axi4nfcs2m;
EastRXNFCM2SxDO : out t_axi4nfcm2s;
EastTXNFCM2SxDI : in t_axi4nfcm2s;
EastTXNFCS2MxDO : out t_axi4nfcs2m;
SouthRXNFCM2SxDO : out t_axi4nfcm2s;
SouthTXNFCM2SxDI : in t_axi4nfcm2s;
SouthTXNFCS2mxDO : out t_axi4nfcs2m;
WestRXNFCM2SxDO : out t_axi4nfcm2s;
WestTXNFCM2SxDI : in t_axi4nfcm2s;
WestTXNFCS2MxDO : out t_axi4nfcs2m;
AuroraCtrlxDI : in t_aurora_control; AuroraCtrlxDI : in t_aurora_control;
AuroraStatusxDO : out t_aurora_status; AuroraStatusxDO : out t_aurora_status;
AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0); AuroraDRPM2SxDI : in t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0);
...@@ -325,58 +337,86 @@ architecture arch of scalp_firmware is ...@@ -325,58 +337,86 @@ architecture arch of scalp_firmware is
-- Signals -- Signals
-- Clocks -- Clocks
-- Processing system clock -- Processing system clock
signal PSSysClkxC : std_logic := '0'; signal PSSysClkxC : std_logic := '0';
-- GTP Clocks -- GTP Clocks
-- signal GTPRefClk0xC : std_logic := '0'; -- signal GTPRefClk0xC : std_logic := '0';
-- signal GTPRefClk1xC : std_logic := '0'; -- signal GTPRefClk1xC : std_logic := '0';
signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK; signal GTRefClk0DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK; signal GTRefClk1DiffxC : t_gtp_diff_ref_clk := C_NO_GTP_DIFF_REF_CLK;
-- Resets -- Resets
-- Processing system reset -- Processing system reset
signal PSSysResetxR : std_logic := '0'; signal PSSysResetxR : std_logic := '0';
-- Scalp Aurora Phy -- Scalp Aurora Phy
signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK; signal GTRefClk0xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK; signal GTRefClk1xC : t_gt_ref_slave_clk := C_GT_REF_NO_SLAVE_CLK;
signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK; signal AuroraClkSlavexC : t_aurora_slave_clk := C_AURORA_NO_SLAVE_CLK;
signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK; signal AuroraClkMasterxC : t_aurora_master_clk := C_AURORA_NO_MASTER_CLK;
signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET; signal AuroraResetSlavexR : t_aurora_slave_reset := C_AURORA_NO_SLAVE_RESET;
signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET; signal AuroraResetMasterLinkxR : t_aurora_master_link_reset := C_AURORA_NO_MASTER_LINK_RESET;
signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX; signal GTPFromNorthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX; signal GTPToNorthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX; signal GTPFromEastxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX; signal GTPToEastxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX; signal GTPFromSouthxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX; signal GTPToSouthxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX; signal GTPFromWestxD : t_aurora_gtp_diff_io_rx := C_AURORA_NO_GTP_DIFF_IO_RX;
signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX; signal GTPToWestxD : t_aurora_gtp_diff_io_tx := C_AURORA_NO_GTP_DIFF_IO_TX;
signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal NorthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal NorthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M; signal NorthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal EastRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal EastTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M; signal EastTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal SouthRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal SouthTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M; signal SouthTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal WestRXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S; signal WestTXM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M; signal WestTXS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX; signal NorthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX; signal NorthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX; signal EastRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX; signal EastRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX; signal SouthRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX; signal SouthRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX; signal WestRXfromPhyTXfromFifoM2SxD : t_axi4m2s := C_NO_AXI4_M2S;
signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX; signal WestRXfromPhyTXfromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX; signal NorthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX; signal EastRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX; signal SouthRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX; signal WestRXFromFifoS2MxD : t_axi4s2m := C_NO_AXI4_S2M;
signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL; signal NorthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS; signal NorthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S); signal NorthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M); signal EastRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
signal EastTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
signal EastTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
signal SouthRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
signal SouthTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
signal SouthTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
signal WestRXUFCM2SxD : t_axi4ufcm2s_rx := C_NO_AXI4_UFC_M2S_RX;
signal WestTXUFCM2SxD : t_axi4ufcm2s_tx := C_NO_AXI4_UFC_M2S_TX;
signal WestTXUFCS2MxD : t_axi4ufcs2m_tx := C_NO_AXI4_UFC_S2M_TX;
signal NorthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal NorthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal NorthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
signal EastRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal EastTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal EastTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
signal SouthRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal SouthTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal SouthTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
signal WestRXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal WestTXNFCM2SxD : t_axi4nfcm2s := C_NO_AXI4_NFC_M2S;
signal WestTXNFCS2MxD : t_axi4nfcs2m := C_NO_AXI4_NFC_S2M;
signal AuroraCtrlxD : t_aurora_control := C_AURORA_NO_CONTROL;
signal AuroraStatusxD : t_aurora_status := C_AURORA_NO_STATUS;
signal AuroraDRPM2SxD : t_drpm2s_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_M2S);
signal AuroraDRPS2MxD : t_drps2m_vector((C_NB_GTP_CORE - 1) downto 0) := (others => C_NO_DRP_S2M);
signal NorthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
signal EastFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
signal SouthFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
signal WestFifoStatusxD : t_axi4fifo_status := C_NO_AXI4_FIFO_STATUS;
-- Attributes -- Attributes
attribute mark_debug : string; attribute mark_debug : string;
...@@ -596,6 +636,23 @@ begin ...@@ -596,6 +636,23 @@ begin
WestRXUFCM2SxDO => WestRXUFCM2SxD, WestRXUFCM2SxDO => WestRXUFCM2SxD,
WestTXUFCM2SxDI => WestTXUFCM2SxD, WestTXUFCM2SxDI => WestTXUFCM2SxD,
WestTXUFCS2MxDO => WestTXUFCS2MxD, WestTXUFCS2MxDO => WestTXUFCS2MxD,
-- Axi4 Framing NFC Interface
-- North
NorthRXNFCM2SxDO => NorthRXNFCM2SxD,
NorthTXNFCM2SxDI => NorthTXNFCM2SxD,
NorthTXNFCS2MxDO => NorthTXNFCS2MxD,
-- East
EastRXNFCM2SxDO => EastRXNFCM2SxD,
EastTXNFCM2SxDI => EastTXNFCM2SxD,
EastTXNFCS2MxDO => EastTXNFCS2MxD,
-- South
SouthRXNFCM2SxDO => SouthRXNFCM2SxD,
SouthTXNFCM2SxDI => SouthTXNFCM2SxD,
SouthTXNFCS2mxDO => SouthTXNFCS2mxD,
-- West
WestRXNFCM2SxDO => WestRXNFCM2SxD,
WestTXNFCM2SxDI => WestTXNFCM2SxD,
WestTXNFCS2MxDO => WestTXNFCS2MxD,
-- Aurora Ctrl + Status -- Aurora Ctrl + Status
AuroraCtrlxDI => AuroraCtrlxD, AuroraCtrlxDI => AuroraCtrlxD,
AuroraStatusxDO => AuroraStatusxD, AuroraStatusxDO => AuroraStatusxD,
...@@ -603,6 +660,340 @@ begin ...@@ -603,6 +660,340 @@ begin
AuroraDRPM2SxDI => (others => C_NO_DRP_M2S), AuroraDRPM2SxDI => (others => C_NO_DRP_M2S),
AuroraDRPS2MxDO => open); AuroraDRPS2MxDO => open);
RXFifoxB : block is
signal RXFifoRstxRAN : std_ulogic := '0';
begin -- block RXFifoxB
RXFifoRstxAS : RXFifoRstxRAN <= not AuroraClkMasterxC.PllNotLockedxS;
ScalpAuroraPhyRXFifoxI : entity work.scalp_aurora_phy_rx_fifo
port map (
-- Clocks and reset
RXClkxCI => AuroraClkMasterxC.UserClkxC,
TXClkxCI => AuroraClkMasterxC.UserClkxC,
RXRstxRANI => RXFifoRstxRAN,
-- North
-- Fifo RX Side
NorthRXM2SxDI => NorthRXM2SxD,
NorthRXS2MxDO => NorthRXFromFifoS2MxD,
-- Fifo TX Side
NorthTXM2SxDO => NorthRXfromPhyTXfromFifoM2SxD,
NorthTXS2MxDI => NorthRXfromPhyTXfromFifoS2MxD,
NorthFifoStatusxDO => NorthFifoStatusxD,
-- East
-- Fifo RX Side
EastRXM2SxDI => EastRXM2SxD,
EastRXS2MxDO => EastRXFromFifoS2MxD,
-- Fifo TX Side
EastTXM2SxDO => EastRXfromPhyTXfromFifoM2SxD,
EastTXS2MxDI => EastRXfromPhyTXfromFifoS2MxD,
EastFifoStatusxDO => EastFifoStatusxD,
-- South
-- Fifo RX Side
SouthRXM2SxDI => SouthRXM2SxD,
SouthRXS2MxDO => SouthRXFromFifoS2MxD,
-- Fifo TX Side
SouthTXM2SxDO => SouthRXfromPhyTXfromFifoM2SxD,
SouthTXS2MxDI => SouthRXfromPhyTXfromFifoS2MxD,
SouthFifoStatusxDO => SouthFifoStatusxD,
-- West
-- Fifo RX Side
WestRXM2SxDI => WestRXM2SxD,
WestRXS2MxDO => WestRXFromFifoS2MxD,
-- Fifo TX Side
WestTXM2SxDO => WestRXfromPhyTXfromFifoM2SxD,
WestTXS2MxDI => WestRXfromPhyTXfromFifoS2MxD,
WestFifoStatusxDO => WestFifoStatusxD);
end block RXFifoxB;
BackPressurexB : block is
signal NorthSendXOFFxSN : std_ulogic := '0';
signal NorthSendXOFFxSP : std_ulogic := '0';
signal EastSendXOFFxSN : std_ulogic := '0';
signal EastSendXOFFxSP : std_ulogic := '0';
signal SouthSendXOFFxSN : std_ulogic := '0';
signal SouthSendXOFFxSP : std_ulogic := '0';
signal WestSendXOFFxSN : std_ulogic := '0';
signal WestSendXOFFxSP : std_ulogic := '0';
-- North
signal NorthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
signal NorthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
signal NorthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal NorthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal NorthNFCValidxSN : std_ulogic := '0';
signal NorthNFCValidxSP : std_ulogic := '0';
-- East
signal EastNFCStatexDN : t_nfc_states := C_NFC_IDLE;
signal EastNFCStatexDP : t_nfc_states := C_NFC_IDLE;
signal EastNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal EastNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal EastNFCValidxSN : std_ulogic := '0';
signal EastNFCValidxSP : std_ulogic := '0';
-- South
signal SouthNFCStatexDN : t_nfc_states := C_NFC_IDLE;
signal SouthNFCStatexDP : t_nfc_states := C_NFC_IDLE;
signal SouthNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal SouthNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal SouthNFCValidxSN : std_ulogic := '0';
signal SouthNFCValidxSP : std_ulogic := '0';
-- West
signal WestNFCStatexDN : t_nfc_states := C_NFC_IDLE;
signal WestNFCStatexDP : t_nfc_states := C_NFC_IDLE;
signal WestNFCDataxDN : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal WestNFCDataxDP : std_ulogic_vector((C_AXI4_NFC_DATA_SIZE - 1) downto 0) := (others => '0');
signal WestNFCValidxSN : std_ulogic := '0';
signal WestNFCValidxSP : std_ulogic := '0';
begin -- block BackPressurexB
NorthSendXONxAS : NorthSendXOFFxSN <= '1' when
(NorthRXFromFifoS2MxD.ReadyxS = '0') or
(NorthFifoStatusxD.ProgFullxS = '1') else
'0';
EastSendXONxAS : EastSendXOFFxSN <= '1' when
(EastRXFromFifoS2MxD.ReadyxS = '0') or
(EastFifoStatusxD.ProgFullxS = '1') else
'0';
SouthSendXONxAS : SouthSendXOFFxSN <= '1' when
(SouthRXFromFifoS2MxD.ReadyxS = '0') or
(SouthFifoStatusxD.ProgFullxS = '1') else
'0';
WestSendXONxAS : WestSendXOFFxSN <= '1' when
(WestRXFromFifoS2MxD.ReadyxS = '0') or
(WestFifoStatusxD.ProgFullxS = '1') else
'0';
-- NFC Data and valid signals
NorthNFCDataxAS : NorthTXNFCM2SxD.DataxD <= NorthNFCDataxDP;
NorthNFCValidxAS : NorthTXNFCM2SxD.ValidxS <= NorthNFCValidxSP;
EastNFCDataxAS : EastTXNFCM2SxD.DataxD <= EastNFCDataxDP;
EastNFCValidxAS : EastTXNFCM2SxD.ValidxS <= EastNFCValidxSP;
SouthNFCDataxAS : SouthTXNFCM2SxD.DataxD <= SouthNFCDataxDP;
SouthNFCValidxAS : SouthTXNFCM2SxD.ValidxS <= SouthNFCValidxSP;
WestNFCDataxAS : WestTXNFCM2SxD.DataxD <= WestNFCDataxDP;
WestNFCValidxAS : WestTXNFCM2SxD.ValidxS <= WestNFCValidxSP;
UpdateRegxP : process (AuroraClkMasterxC.PllNotLockedxS,
AuroraClkMasterxC.UserClkxC) is
begin -- process UpdateRegxP
if not AuroraClkMasterxC.PllNotLockedxS then
NorthSendXOFFxSP <= '0';
EastSendXOFFxSP <= '0';
SouthSendXOFFxSP <= '0';
WestSendXOFFxSP <= '0';
NorthNFCStatexDP <= C_NFC_IDLE;
NorthNFCDataxDP <= (others => '0');
NorthNFCValidxSP <= '0';
EastNFCStatexDP <= C_NFC_IDLE;
EastNFCDataxDP <= (others => '0');
EastNFCValidxSP <= '0';
SouthNFCStatexDP <= C_NFC_IDLE;
SouthNFCDataxDP <= (others => '0');
SouthNFCValidxSP <= '0';
WestNFCStatexDP <= C_NFC_IDLE;
WestNFCDataxDP <= (others => '0');
WestNFCValidxSP <= '0';
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
NorthSendXOFFxSP <= NorthSendXOFFxSN;
EastSendXOFFxSP <= EastSendXOFFxSN;
SouthSendXOFFxSP <= SouthSendXOFFxSN;
WestSendXOFFxSP <= WestSendXOFFxSN;
NorthNFCStatexDP <= NorthNFCStatexDN;
NorthNFCDataxDP <= NorthNFCDataxDN;
NorthNFCValidxSP <= NorthNFCValidxSN;
EastNFCStatexDP <= EastNFCStatexDN;
EastNFCDataxDP <= EastNFCDataxDN;
EastNFCValidxSP <= EastNFCValidxSN;
SouthNFCStatexDP <= SouthNFCStatexDN;
SouthNFCDataxDP <= SouthNFCDataxDN;
SouthNFCValidxSP <= SouthNFCValidxSN;
WestNFCStatexDP <= WestNFCStatexDN;
WestNFCDataxDP <= WestNFCDataxDN;
WestNFCValidxSP <= WestNFCValidxSN;
end if;
end process UpdateRegxP;
NorthNFCStatexP : process (NorthNFCDataxDP, NorthNFCStatexDP,
NorthNFCValidxSP, NorthSendXOFFxSN,
NorthSendXOFFxSP,
NorthTXUFCS2MxD.ReadyxS) is
begin -- process NorthNFCStatexP
-- Default values
NorthNFCStatexDN <= NorthNFCStatexDP;
NorthNFCDataxDN <= NorthNFCDataxDP;
NorthNFCValidxSN <= NorthNFCValidxSP;
case NorthNFCStatexDP is
when C_NFC_IDLE =>
NorthNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
if NorthSendXOFFxSP = '0' and NorthSendXOFFxSN = '1' then
NorthNFCDataxDN <= C_NFC_XOFF;
NorthNFCValidxSN <= '1';
NorthNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
if NorthSendXOFFxSP = '1' and NorthSendXOFFxSN = '0' then
NorthNFCDataxDN <= C_NFC_XON;
NorthNFCValidxSN <= '1';
NorthNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
if NorthTXUFCS2MxD.ReadyxS = '1' then
NorthNFCValidxSN <= '0';
NorthNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
if NorthTXUFCS2MxD.ReadyxS = '1' then
NorthNFCValidxSN <= '0';
NorthNFCStatexDN <= C_NFC_IS_XOFF;
end if;
when others => null;
end case;
end process NorthNFCStatexP;
EastNFCStatexP : process (EastNFCDataxDP, EastNFCStatexDP,
EastNFCValidxSP, EastSendXOFFxSN,
EastSendXOFFxSP,
EastTXUFCS2MxD.ReadyxS) is
begin -- process EastNFCStatexP
-- Default values
EastNFCStatexDN <= EastNFCStatexDP;
EastNFCDataxDN <= EastNFCDataxDP;
EastNFCValidxSN <= EastNFCValidxSP;
case EastNFCStatexDP is
when C_NFC_IDLE =>
EastNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
if EastSendXOFFxSP = '0' and EastSendXOFFxSN = '1' then
EastNFCDataxDN <= C_NFC_XOFF;
EastNFCValidxSN <= '1';
EastNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
if EastSendXOFFxSP = '1' and EastSendXOFFxSN = '0' then
EastNFCDataxDN <= C_NFC_XON;
EastNFCValidxSN <= '1';
EastNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
if EastTXUFCS2MxD.ReadyxS = '1' then
EastNFCValidxSN <= '0';
EastNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
if EastTXUFCS2MxD.ReadyxS = '1' then
EastNFCValidxSN <= '0';
EastNFCStatexDN <= C_NFC_IS_XOFF;
end if;
when others => null;
end case;
end process EastNFCStatexP;
SouthNFCStatexP : process (SouthNFCDataxDP, SouthNFCStatexDP,
SouthNFCValidxSP, SouthSendXOFFxSN,
SouthSendXOFFxSP,
SouthTXUFCS2MxD.ReadyxS) is
begin -- process SouthNFCStatexP
-- Default values
SouthNFCStatexDN <= SouthNFCStatexDP;
SouthNFCDataxDN <= SouthNFCDataxDP;
SouthNFCValidxSN <= SouthNFCValidxSP;
case SouthNFCStatexDP is
when C_NFC_IDLE =>
SouthNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
if SouthSendXOFFxSP = '0' and SouthSendXOFFxSN = '1' then
SouthNFCDataxDN <= C_NFC_XOFF;
SouthNFCValidxSN <= '1';
SouthNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
if SouthSendXOFFxSP = '1' and SouthSendXOFFxSN = '0' then
SouthNFCDataxDN <= C_NFC_XON;
SouthNFCValidxSN <= '1';
SouthNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
if SouthTXUFCS2MxD.ReadyxS = '1' then
SouthNFCValidxSN <= '0';
SouthNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
if SouthTXUFCS2MxD.ReadyxS = '1' then
SouthNFCValidxSN <= '0';
SouthNFCStatexDN <= C_NFC_IS_XOFF;
end if;
when others => null;
end case;
end process SouthNFCStatexP;
WestNFCStatexP : process (WestNFCDataxDP, WestNFCStatexDP,
WestNFCValidxSP, WestSendXOFFxSN,
WestSendXOFFxSP,
WestTXUFCS2MxD.ReadyxS) is
begin -- process WestNFCStatexP
-- Default values
WestNFCStatexDN <= WestNFCStatexDP;
WestNFCDataxDN <= WestNFCDataxDP;
WestNFCValidxSN <= WestNFCValidxSP;
case WestNFCStatexDP is
when C_NFC_IDLE =>
WestNFCStatexDN <= C_NFC_IS_XON;
when C_NFC_IS_XON =>
if WestSendXOFFxSP = '0' and WestSendXOFFxSN = '1' then
WestNFCDataxDN <= C_NFC_XOFF;
WestNFCValidxSN <= '1';
WestNFCStatexDN <= C_NFC_SEND_XOFF;
end if;
when C_NFC_IS_XOFF =>
if WestSendXOFFxSP = '1' and WestSendXOFFxSN = '0' then
WestNFCDataxDN <= C_NFC_XON;
WestNFCValidxSN <= '1';
WestNFCStatexDN <= C_NFC_SEND_XON;
end if;
when C_NFC_SEND_XON =>
if WestTXUFCS2MxD.ReadyxS = '1' then
WestNFCValidxSN <= '0';
WestNFCStatexDN <= C_NFC_IS_XON;
end if;
when C_NFC_SEND_XOFF =>
if WestTXUFCS2MxD.ReadyxS = '1' then
WestNFCValidxSN <= '0';
WestNFCStatexDN <= C_NFC_IS_XOFF;
end if;
when others => null;
end case;
end process WestNFCStatexP;
end block BackPressurexB;
end block GTPhyxB; end block GTPhyxB;
DebugxB : block is DebugxB : block is
...@@ -646,20 +1037,20 @@ begin ...@@ -646,20 +1037,20 @@ begin
port map ( port map (
clk => AuroraClkMasterxC.UserClkxC, clk => AuroraClkMasterxC.UserClkxC,
-- North -- North
probe_in0 => NorthRXM2SxD.DataxD, -- 32 bits probe_in0 => NorthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
probe_in1(0) => NorthRXM2SxD.ValidxS, probe_in1(0) => NorthRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in2(0) => NorthTXS2MxD.ReadyxS, probe_in2(0) => NorthTXS2MxD.ReadyxS,
-- East -- East
probe_in3 => EastRXM2SxD.DataxD, -- 32 bits probe_in3 => EastRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
probe_in4(0) => EastRXM2SxD.ValidxS, probe_in4(0) => EastRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in5(0) => EastTXS2MxD.ReadyxS, probe_in5(0) => EastTXS2MxD.ReadyxS,
-- South -- South
probe_in6 => SouthRXM2SxD.DataxD, -- 32 bits probe_in6 => SouthRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
probe_in7(0) => SouthRXM2SxD.ValidxS, probe_in7(0) => SouthRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in8(0) => SouthTXS2MxD.ReadyxS, probe_in8(0) => SouthTXS2MxD.ReadyxS,
-- West -- West
probe_in9 => WestRXM2SxD.DataxD, -- 32 bits probe_in9 => WestRXfromPhyTXfromFifoM2SxD.DataxD, -- 32 bits
probe_in10(0) => WestRXM2SxD.ValidxS, probe_in10(0) => WestRXfromPhyTXfromFifoM2SxD.ValidxS,
probe_in11(0) => WestTXS2MxD.ReadyxS, probe_in11(0) => WestTXS2MxD.ReadyxS,
probe_out0(0) => CntRstxR); probe_out0(0) => CntRstxR);
......
designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
+ 1
− 1
View file @ 997921ee
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2019.2 -- Tool version: 2019.2
-- Description: Testbench for scalp_firmware -- Description: Testbench for scalp_firmware
-- --
-- Last update: 2020-10-13 13:10:02 -- Last update: 2020-11-07 09:14:14
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
......
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