Updated the scalp_firmware reference design with some corrections on back...

Updated the scalp_firmware reference design with some corrections on back pressure management. Back pressure management is external to the IP core scalp_aurora_pyh. The next update is to integrate it to the IP core.

designs/vivado/scalp_firmware/2019.2/src/constrs/debug.xdc

-
-create_debug_core u_ila_0 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
-set_property port_width 1 [get_debug_ports u_ila_0/clk]
-connect_debug_port u_ila_0/clk [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPyhxI/ClkRstxB.AuroraClockModulexI/AuroraClkxCO[InitClkxC]}]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
-set_property port_width 4 [get_debug_ports u_ila_0/probe0]
-connect_debug_port u_ila_0/probe0 [get_nets [list {AuroraResetMasterLinkxR[LinkResetxR][0]} {AuroraResetMasterLinkxR[LinkResetxR][1]} {AuroraResetMasterLinkxR[LinkResetxR][2]} {AuroraResetMasterLinkxR[LinkResetxR][3]}]]
-create_debug_core u_ila_1 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_1]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
-set_property port_width 1 [get_debug_ports u_ila_1/clk]
-connect_debug_port u_ila_1/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPyhxI/ClkRstxB.AuroraClockModulexI/CLK]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_1/probe0]
-set_property port_width 4 [get_debug_ports u_ila_1/probe0]
-connect_debug_port u_ila_1/probe0 [get_nets [list {AuroraResetMasterLinkxR[SystemResetxR][0]} {AuroraResetMasterLinkxR[SystemResetxR][1]} {AuroraResetMasterLinkxR[SystemResetxR][2]} {AuroraResetMasterLinkxR[SystemResetxR][3]}]]
-create_debug_core u_ila_2 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_2]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
-set_property port_width 1 [get_debug_ports u_ila_2/clk]
-connect_debug_port u_ila_2/clk [get_nets [list ProgrammableLogicxB.PllClocksxB.ScalpAuroraPllxI/inst/InitClkxCO]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe0]
-set_property port_width 1 [get_debug_ports u_ila_2/probe0]
-connect_debug_port u_ila_2/probe0 [get_nets [list {AuroraResetSlavexR[GTResetxR]}]]
-create_debug_port u_ila_2 probe
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_2/probe1]
-set_property port_width 1 [get_debug_ports u_ila_2/probe1]
-connect_debug_port u_ila_2/probe1 [get_nets [list {AuroraResetSlavexR[ResetxR]}]]
-create_debug_core u_ila_3 ila
-set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
-set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_3]
-set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3]
-set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3]
-set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_3]
-set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
-set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
-set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
-set_property port_width 1 [get_debug_ports u_ila_3/clk]
-connect_debug_port u_ila_3/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_3/probe0]
-set_property port_width 1 [get_debug_ports u_ila_3/probe0]
-connect_debug_port u_ila_3/probe0 [get_nets [list PSSysResetxR]]
-set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
-set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
-set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
-connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]

designs/vivado/scalp_firmware/2019.2/src/constrs/scalp_firmware.xdc

@@ -246,3 +246,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
 
 
 
+

designs/vivado/scalp_firmware/2019.2/src/constrs/timing_constraints.xdc

@@ -26,3 +26,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
 
 
 
+