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Commit 03b6764e authored by joachim.schmidt's avatar joachim.schmidt
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Addition of all IPS.

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ips/hw/scalp_aurora_phy/src/ip_core/east_channel/doc/aurora_8b10b_v11_1_changelog.txt deleted 100755 → 0
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2019.2:
* Version 11.1 (Rev. 8)
* Revision change in one or more subcores
2019.1.3:
* Version 11.1 (Rev. 7)
* No changes
2019.1.2:
* Version 11.1 (Rev. 7)
* No changes
2019.1.1:
* Version 11.1 (Rev. 7)
* No changes
2019.1:
* Version 11.1 (Rev. 7)
* General: Added support for AKINTEX7 devices
* Revision change in one or more subcores
2018.3.1:
* Version 11.1 (Rev. 6)
* No changes
2018.3:
* Version 11.1 (Rev. 6)
* General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
* General: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
* Revision change in one or more subcores
2018.2:
* Version 11.1 (Rev. 5)
* Bug Fix: Fixed display only issue showing improper clock frequencies for tx_out_clk and sync_clk in IPI flow for GTP devices.
* Revision change in one or more subcores
2018.1:
* Version 11.1 (Rev. 4)
* Bug Fix: Fixed the default tie-off values for rxlpmen port as per INS_LOSS_NYQ and RX_EQ_MODE selection
* Bug Fix: Fixed a bug that generated unexpected error messages during re-customization of IP in IP Integrator
* Other: Added support for Artix-7 XA7A12TCPG238/CSG325 and XA7A25TCPG238/CSG325 devices
* Revision change in one or more subcores
2017.4:
* Version 11.1 (Rev. 3)
* General: Added support for CPG238 packages in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
* Revision change in one or more subcores
2017.3:
* Version 11.1 (Rev. 2)
* General: GTP attribute update in XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
* General: Standard CC logic is enabled after lane-up itself instead of waiting till channel-up condition
* General: Added optional parameter C_DOUBLE_GTRXRESET to assert additional reset for handling errors during lane initialisation in duplex links with very high ppm differences
* General: Updated display values of RX_TERMINATION_PROG_VALUE for UltraScale+ devices to match Xilinx UltraScale Architecture Transceivers user guides
* Revision change in one or more subcores
2017.2:
* Version 11.1 (Rev. 1)
* Bug Fix: Unused gtrxresetseq drp signals removed from TX-simplex based designs
* Other: UltraScale GT Wizard version upgrade.
2017.1:
* Version 11.1
* New Feature: US GT Wizard Instance can be brought out of Aurora IP for UltraScale devices
* Other: gt_powergood from US GT Wizard is made an output port on Aurora core when GT is inside Aurora IP
* Other: gt_powergood from US GT Wizard is brought to gt wrapper in example design when the GT is in example design, outside Aurora IP
* Revision change in one or more subcores
2016.4:
* Version 11.0 (Rev. 7)
* General: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti devices
* Revision change in one or more subcores
2016.3:
* Version 11.0 (Rev. 6)
* Bug Fix: Fixed issue in failure due to floating point precision difference of gt_refclk in validate BD design in IPI
* Bug Fix: Fixed TXDIFFCTRL and DMONITOROUT port widths for UltraScale devices in IP symbol
* Feature Enhancement: Added Advanced RX GT Options selection in GUI
* Other: Added support for XC7A12T, XC7A12Ti, XC7A25T, XC7A25Ti, XC7Z012S devices
* Revision change in one or more subcores
2016.2:
* Version 11.0 (Rev. 5)
* Fixed Artix7 periodic channel up toggle issue
* Revision change in one or more subcores
2016.1:
* Version 11.0 (Rev. 4)
* Fixed preserving Equalizer selection issue when additional transceiver ports option is enabled
* Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
* Revision change in one or more subcores
2015.4.2:
* Version 11.0 (Rev. 3)
* No changes
2015.4.1:
* Version 11.0 (Rev. 3)
* No changes
2015.4:
* Version 11.0 (Rev. 3)
* Added support for new speedgrades of XQ7K325T and XQ7K410T devices
* Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices
* Added support for new speedgrade of XQ7A050T, XQ7A100T and XQ7A200T devices
* Revision change in one or more subcores
2015.3:
* Version 11.0 (Rev. 2)
* Updated RTL to fix CDC warnings
* Added support for UltraScale+ devices
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
2015.2.1:
* Version 11.0 (Rev. 1)
* No changes
2015.2:
* Version 11.0 (Rev. 1)
* Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices
* BUFG removed on DRP Clock input
* TXPMARESETDONE used in rxstartupfsm for GTP RX-onlySimplex configuration
* set_false_path constrain on synchronizers updated
2015.1:
* Version 11.0
* Added support for 7 Series devices with FFV and FBV Pb-Free RoHs package
* Added txinhibit and pcsrsvdin optional transceiver control and status ports
* Both reset and gt_reset ports made asynchronous to the core
* Standard CC module made part of IP, do_cc and warn_cc ports removed
* Flow control ports grouped into AXI4 Stream interfaces
* Control and status ports are grouped as display interfaces
* Added support for single ended clocking option to INIT_CLK and GTREFCLK
* Added support for contiguous lane selection for Ultrascale devices
* CRC resource utilization optimized
* GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator
* Line rate value restricted to 4 decimal digits for Ultrascale devices
* INIT clock frequency value restricted to 6 decimal digits
2014.4.1:
* Version 10.3 (Rev. 2)
* Ultrascale GT Wizard version updated
2014.4:
* Version 10.3 (Rev. 1)
* Added support for new XC7A15T, XC7A15TI, XA7A15T, XC7A35TI, XC7A50TI, XC7A75TI, XC7A100TI and XC7A200TI devices
* Added support for XC7Z015I, XC7Z030I, XC7Z045I, XC7Z035, XC7Z035I and XC7Z100I devices
* Added support for XC7K160TI, XC7K325TI, XC7K355TI, XC7K410TI, XC7K420TI and XC7K480TI devices
* BUFG added to DRP Clock input
* Line rate range for -2L speed grade 1.0V Artix devices updated to 6.25Gbps
* Location constraint changed for Xilinx Evaluation platform boards
2014.3:
* Version 10.3
* Ultrascale GT Wizard version updated
* Added support for new Ultrascale devices
* Added support for XQ7A50 devices
* Added support for XA7Z030 devices
* Added support for user configurable DRP clock and INIT clock through IP GUI
* Added C_EXAMPLE_SIMULATION parameter for post synthesis/implementation simulation speedup
* set_max_delay constrain changed to set_false_path constrains to destination flops
* XDCs compliant with updated timing constraining guidelines
* Added support for Xilinx Evaluation platform boards
* User selectable option enabled for GT DRP interface in IPI systems
* Added support for auto propagate to INIT and DRP clock in IPI systems
* Fixed gt_dmonitorout_out data width mismatch issue for Zynq devices
* Differential INIT clock input added to Ultrascale example design
* Addressed CPLL power down circuit requirement for 7 series Transceivers - refer AR
* GT startup fsms updated to be complain with 7 Series GT Wizard
* Addressed update to GTH/GTP Production RX reset sequence implementation- refer AR
* Parameter declaration issue with IES simulator addressed
2014.2:
* Version 10.2 (Rev. 1)
* Ultrascale GT Wizard version change
* Added support for XQ7Z045 RF900 devices
* Fixed hold violation timing issues in Ultrascale device based designs
* Updated channel bonding levels logic for >= 13 lanes in 4 byte mode
* Fixed gt0_dmonitorout_out port width for GTX devices in transceiver debug ports
* Free running INIT CLK is connected to VIO core in example design
* Fixed latch inference issue in crc modules for VHDL designs
* Updated CLK_COR_MIN_LAT and CLK_COR_MAX_LAT values for 16-GT (GTHE3_CHANNEL) in Ultrascale device
2014.1:
* Version 10.2
* Added support for Ultrascale devices
* Added support for XC7Z015, XC7A50T, XC7A35T devices
* Added support for automotive aartix XA7A35, XA7A50T, XA7A75T & XA7A100T devices
* Enhanced support for IP Integrator
* Added Little endian support for data & flow control interfaces as non-default GUI selectable option
* Fixed VHDL syntax issue on rxpmaresetdone_t signal for 7-series based designs
* Updated OOC XDC with all the available clocks for the selected IP configuration
* Fixed TXCRC and RXCRC modules to operate upon valid data and report correct CRC status
* Updated core reset logic with tx_lock synchronization
* Updated the simplex timer values for 7-series production silicon logic updates
* Updated the hot-plug logic to handle clock domain crossing efficiently
* Added recovery mechanism for channel bonding failure
2013.4:
* Version 10.1
* Increased the number of optional transceiver control and status ports
2013.3:
* Version 10.0
* Added support for XC7A75T device
* Added startup FSM integration for 7-series GT reset sequence
* Added GUI option to include or exclude Vivado Labtools support for debug
* Updated line rate for A7 wire bond package devices for speed grade -2 and -3
* Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
* Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Reduced warnings in synthesis and simulation
* Added support for Cadence IES and Synopsys VCS simulators
* Added support for IP Integrator level 0
2013.2:
* Version 9.1
* Artix-7 GTP and Virtex-7 GTH production attributes updates
* XDC constraints processing order changed
* Update for UFC packet drop in back to back data transfer
* XQ7Z030-RB484 device support
2013.1:
* Version 9.0
* Lower case IP level ports
* Hot-plug timer update
* CDC fixes
* New reset sequence for GTRXRESET in Artix-7 GTP Production silicon
* New reset sequence for GTRXRESET in Virtex-7 GTH Production silicon
* Out-of-context (OOC) flow support
* Zynq-7000 family support
2012.4:
* Version 8.3 (Rev. 1)
* Artix-7 IES silicon support
* Autoupgrade feature
2012.3:
* Version 8.3
* Artix-7 family support
2012.2:
* Version 8.2
* Virtex-7 HT device support
* CRC feature addition
* Hot-plug support for 7-series
* XSIM simulator support
* Native Vivado release
(c) Copyright 2010 - 2019 Xilinx, Inc. All rights reserved.
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of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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(including loss of data, profits, goodwill, or any type of
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by a third party) even if such damage or loss was
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possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
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------------------------------------------------------------------------------/
-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity east_channel is
port (
-- AXI TX Interface
s_axi_tx_tdata : in std_logic_vector(0 to 31);
s_axi_tx_tvalid : in std_logic;
s_axi_tx_tready : out std_logic;
s_axi_tx_tkeep : in std_logic_vector(0 to 3);
s_axi_tx_tlast : in std_logic;
-- AXI RX Interface
m_axi_rx_tdata : out std_logic_vector(0 to 31);
m_axi_rx_tvalid : out std_logic;
m_axi_rx_tkeep : out std_logic_vector(0 to 3);
m_axi_rx_tlast : out std_logic;
-- User Flow Control TX Interface
s_axi_ufc_tx_tvalid : in std_logic;
s_axi_ufc_tx_tdata : in std_logic_vector(0 to 2);
s_axi_ufc_tx_tready : out std_logic;
-- User Flow Control RX Inteface
m_axi_ufc_rx_tdata : out std_logic_vector(0 to 31);
m_axi_ufc_rx_tkeep : out std_logic_vector(0 to 3);
m_axi_ufc_rx_tvalid : out std_logic;
m_axi_ufc_rx_tlast : out std_logic;
-- GT Serial I/O
rxp : in std_logic_vector(0 downto 0);
rxn : in std_logic_vector(0 downto 0);
txp : out std_logic_vector(0 downto 0);
txn : out std_logic_vector(0 downto 0);
-- GT Reference Clock Interface
gt_refclk1 : in std_logic;
-- Error Detection Interface
frame_err : out std_logic;
hard_err : out std_logic;
soft_err : out std_logic;
channel_up : out std_logic;
lane_up : out std_logic_vector(0 downto 0);
-- System Interface
user_clk : in std_logic;
sync_clk : in std_logic;
reset : in std_logic;
power_down : in std_logic;
loopback : in std_logic_vector(2 downto 0);
gt_reset : in std_logic;
tx_lock : out std_logic;
sys_reset_out : out std_logic;
init_clk_in : in std_logic;
tx_resetdone_out : out std_logic;
rx_resetdone_out : out std_logic;
link_reset_out : out std_logic;
--DRP Ports
drpclk_in : in std_logic;
drpaddr_in : in std_logic_vector(8 downto 0);
drpdi_in : in std_logic_vector(15 downto 0);
drpdo_out : out std_logic_vector(15 downto 0);
drpen_in : in std_logic;
drprdy_out : out std_logic;
drpwe_in : in std_logic;
gt_common_reset_out : out std_logic;
--____________________________COMMON PORTS_______________________________{
gt0_pll0refclklost_in : in std_logic;
quad1_common_lock_in : in std_logic;
------------------------- Channel - Ref Clock Ports ------------------------
GT0_PLL0OUTCLK_IN : in std_logic;
GT0_PLL1OUTCLK_IN : in std_logic;
GT0_PLL0OUTREFCLK_IN : in std_logic;
GT0_PLL1OUTREFCLK_IN : in std_logic;
--____________________________COMMON PORTS_______________________________}
tx_out_clk : out std_logic;
pll_not_locked : in std_logic
);
end east_channel;
architecture STRUCTURE of east_channel is
attribute core_generation_info : string;
attribute core_generation_info of STRUCTURE : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
component east_channel_core
port (
-- TX Stream Interface
S_AXI_TX_TDATA : in std_logic_vector(0 to 31);
S_AXI_TX_TKEEP : in std_logic_vector(0 to 3);
S_AXI_TX_TVALID : in std_logic;
S_AXI_TX_TREADY : out std_logic;
S_AXI_TX_TLAST : in std_logic;
-- RX Stream Interface
M_AXI_RX_TDATA : out std_logic_vector(0 to 31);
M_AXI_RX_TKEEP : out std_logic_vector(0 to 3);
M_AXI_RX_TVALID : out std_logic;
M_AXI_RX_TLAST : out std_logic;
-- User Flow Control TX Interface
S_AXI_UFC_TX_REQ : in std_logic;
S_AXI_UFC_TX_MS : in std_logic_vector(0 to 2);
S_AXI_UFC_TX_ACK : out std_logic;
-- User Flow Control RX Inteface
M_AXI_UFC_RX_TDATA : out std_logic_vector(0 to 31);
M_AXI_UFC_RX_TKEEP : out std_logic_vector(0 to 3);
M_AXI_UFC_RX_TVALID : out std_logic;
M_AXI_UFC_RX_TLAST : out std_logic;
-- GTX Serial I/O
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic;
-- GT Reference Clock Interface
gt_refclk1 : in std_logic;
-- Error Detection Interface
HARD_ERR : out std_logic;
SOFT_ERR : out std_logic;
-- Status
CHANNEL_UP : out std_logic;
LANE_UP : out std_logic;
FRAME_ERR : out std_logic;
-- Clock Compensation Control Interface
-- System Interface
USER_CLK : in std_logic;
SYNC_CLK : in std_logic;
GT_RESET : in std_logic;
RESET : in std_logic;
sys_reset_out : out std_logic;
POWER_DOWN : in std_logic;
LOOPBACK : in std_logic_vector(2 downto 0);
TX_OUT_CLK : out std_logic;
INIT_CLK_IN : in std_logic;
PLL_NOT_LOCKED : in std_logic;
TX_RESETDONE_OUT : out std_logic;
RX_RESETDONE_OUT : out std_logic;
LINK_RESET_OUT : out std_logic;
drpclk_in : in std_logic;
DRPADDR_IN : in std_logic_vector(8 downto 0);
DRPDI_IN : in std_logic_vector(15 downto 0);
DRPDO_OUT : out std_logic_vector(15 downto 0);
DRPEN_IN : in std_logic;
DRPRDY_OUT : out std_logic;
DRPWE_IN : in std_logic;
gt_common_reset_out : out std_logic;
--____________________________COMMON PORTS_______________________________{
gt0_pll0refclklost_in : in std_logic;
quad1_common_lock_in : in std_logic;
------------------------- Channel - Ref Clock Ports ------------------------
GT0_PLL0OUTCLK_IN : in std_logic;
GT0_PLL1OUTCLK_IN : in std_logic;
GT0_PLL0OUTREFCLK_IN : in std_logic;
GT0_PLL1OUTREFCLK_IN : in std_logic;
--____________________________COMMON PORTS_______________________________}
TX_LOCK : out std_logic
);
end component;
begin
--*********************************Main Body of Code**********************************
U0 : east_channel_core
port map (
-- AXI TX Interface
s_axi_tx_tdata => s_axi_tx_tdata,
s_axi_tx_tkeep => s_axi_tx_tkeep,
s_axi_tx_tvalid => s_axi_tx_tvalid,
s_axi_tx_tlast => s_axi_tx_tlast,
s_axi_tx_tready => s_axi_tx_tready,
-- AXI RX Interface
m_axi_rx_tdata => m_axi_rx_tdata,
m_axi_rx_tkeep => m_axi_rx_tkeep,
m_axi_rx_tvalid => m_axi_rx_tvalid,
m_axi_rx_tlast => m_axi_rx_tlast,
-- User Flow Control TX Interface
s_axi_ufc_tx_req => s_axi_ufc_tx_tvalid,
s_axi_ufc_tx_ms => s_axi_ufc_tx_tdata,
s_axi_ufc_tx_ack => s_axi_ufc_tx_tready,
-- User Flow Control RX Inteface
m_axi_ufc_rx_tdata => m_axi_ufc_rx_tdata,
m_axi_ufc_rx_tkeep => m_axi_ufc_rx_tkeep,
m_axi_ufc_rx_tvalid => m_axi_ufc_rx_tvalid,
m_axi_ufc_rx_tlast => m_axi_ufc_rx_tlast,
-- GT Serial I/O
rxp => rxp(0),
rxn => rxn(0),
txp => txp(0),
txn => txn(0),
-- GT Reference Clock Interface
gt_refclk1 => gt_refclk1,
-- Error Detection Interface
frame_err => frame_err,
-- Error Detection Interface
hard_err => hard_err,
soft_err => soft_err,
-- Status
channel_up => channel_up,
lane_up => lane_up(0),
-- System Interface
user_clk => user_clk,
sync_clk => sync_clk,
reset => reset,
sys_reset_out => sys_reset_out,
power_down => power_down,
loopback => loopback,
gt_reset => gt_reset,
tx_lock => tx_lock,
init_clk_in => init_clk_in,
pll_not_locked => pll_not_locked,
tx_resetdone_out => tx_resetdone_out,
rx_resetdone_out => rx_resetdone_out,
link_reset_out => link_reset_out,
drpclk_in => drpclk_in,
drpaddr_in => drpaddr_in,
drpen_in => drpen_in,
drpdi_in => drpdi_in,
drprdy_out => drprdy_out,
drpdo_out => drpdo_out,
drpwe_in => drpwe_in,
--------------------{
gt_common_reset_out => gt_common_reset_out,
--____________________________COMMON PORTS_______________________________{
gt0_pll0refclklost_in => gt0_pll0refclklost_in,
quad1_common_lock_in => quad1_common_lock_in,
------------------------- Channel - Ref Clock Ports ------------------------
GT0_PLL0OUTCLK_IN => GT0_PLL0OUTCLK_IN,
GT0_PLL1OUTCLK_IN => GT0_PLL1OUTCLK_IN,
GT0_PLL0OUTREFCLK_IN => GT0_PLL0OUTREFCLK_IN,
GT0_PLL1OUTREFCLK_IN => GT0_PLL1OUTREFCLK_IN,
--____________________________COMMON PORTS_______________________________}
--------------------}
tx_out_clk => tx_out_clk
);
end STRUCTURE;
ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xdc deleted 100644 → 0
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################################################################################
##
## (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##
################################################################################
## east_channel.xdc generated for xc7z015-clg485-2 device
# TXOUTCLK Constraint: Value is selected based on the line rate (5.0 Gbps) and lane width (4-Byte)
create_clock -period 4.0 [get_pins -filter {REF_PIN_NAME=~*TXOUTCLK} -of_objects [get_cells -hierarchical -filter {NAME =~ *gt_wrapper_i*east_channel_multi_gt_i*gt0_east_channel_i*gtpe2_i*}]]
#### CDC Path #####
set_false_path -to [get_pins -filter {REF_PIN_NAME=~*D} -of_objects [get_cells -hierarchical -filter {NAME =~ *east_channel_cdc_to*}]]
####################### GT reference clock LOC (For use in top level design) #######################
# set_property LOC V5 [get_ports GTPQ0_N]
# set_property LOC U5 [get_ports GTPQ0_P]
############################### GT LOC (For use in top level design) ###################################
# set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells aurora_module_i/east_channel_i/U0/gt_wrapper_i/east_channel_multi_gt_i/gt0_east_channel_i/gtpe2_i]
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ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/gt/east_channel_gtrxreset_seq.vhd deleted 100644 → 0
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------------------------------------------------------------------------------/
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY east_channel_gtrxreset_seq IS
port (
RST : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
GTRXRESET_IN : IN std_logic; --Please add a synchroniser if it is not generated in DRPCLK domain.
RXPMARESETDONE: IN std_logic;
GTRXRESET_OUT : OUT std_logic;
STABLE_CLOCK : IN std_logic;
DRPCLK : IN std_logic;
DRPADDR : OUT std_logic_vector(8 downto 0);
DRPDO : IN std_logic_vector(15 downto 0);
DRPDI : OUT std_logic_vector(15 downto 0);
DRPRDY : IN std_logic;
DRPEN : OUT std_logic;
DRPWE : OUT std_logic;
DRP_OP_DONE : OUT std_logic
);
END east_channel_gtrxreset_seq;
ARCHITECTURE Behavioral of east_channel_gtrxreset_seq is
component east_channel_cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end component;
constant DLY : time := 1 ns;
type state_type is (idle,
drp_rd,
wait_rd_data,
wr_16,
wait_wr_done1,
wait_pmareset,
wr_20,
wait_wr_done2);
signal state : state_type := idle;
signal next_state : state_type := idle;
signal gtrxreset_f : std_logic;
signal gtrxreset_s : std_logic;
signal gtrxreset_ss : std_logic;
signal rst_ss : std_logic;
signal rxpmaresetdone_ss : std_logic;
signal rxpmaresetdone_sss : std_logic;
signal rd_data : std_logic_vector(15 downto 0);
signal next_rd_data : std_logic_vector(15 downto 0);
signal pmarstdone_fall_edge: std_logic;
signal gtrxreset_i : std_logic;
signal gtrxreset_o : std_logic;
signal drpen_o : std_logic;
signal drpwe_o : std_logic;
signal drpaddr_o : std_logic_vector(8 downto 0);
signal drpdi_o : std_logic_vector(15 downto 0);
signal drp_op_done_o : std_logic;
signal flag : std_logic :='0';
signal original_rd_data : std_logic_vector(15 downto 0);
BEGIN
flag_gen : PROCESS(DRPCLK)
BEGIN
IF (DRPCLK = '1' and DRPCLK'event) THEN
IF (state = wr_16 or state = wait_pmareset or state = wr_20 or state = wait_wr_done1) THEN
flag <= '1';
ELSIF(state = wait_wr_done2) THEN
flag <= '0';
END IF;
END IF;
END PROCESS flag_gen;
org_data_gen : PROCESS(DRPCLK)
BEGIN
IF (DRPCLK = '1' and DRPCLK'event) THEN
IF ( state = wait_rd_data and DRPRDY = '1' and flag = '0') THEN
original_rd_data <= DRPDO;
END IF;
END IF;
END PROCESS org_data_gen;
rxpmaresetdone_cdc_sync : east_channel_cdc_sync
generic map
(
c_cdc_type => 1 ,
c_flop_input => 0 ,
c_reset_state => 0 ,
c_single_bit => 1 ,
c_vector_width => 2 ,
c_mtbf_stages => 6
)
port map
(
prmry_aclk => '0' ,
prmry_resetn => '1' ,
prmry_in => RXPMARESETDONE ,
prmry_vect_in => "00" ,
scndry_aclk => DRPCLK ,
scndry_resetn => '1' ,
prmry_ack => open ,
scndry_out => rxpmaresetdone_ss ,
scndry_vect_out => open
);
rst_cdc_sync : east_channel_cdc_sync
generic map
(
c_cdc_type => 1 ,
c_flop_input => 1 ,
c_reset_state => 0 ,
c_single_bit => 1 ,
c_vector_width => 2 ,
c_mtbf_stages => 6
)
port map
(
prmry_aclk => STABLE_CLOCK ,
prmry_resetn => '1' ,
prmry_in => RST ,
prmry_vect_in => "00" ,
scndry_aclk => DRPCLK ,
scndry_resetn => '1' ,
prmry_ack => open ,
scndry_out => rst_ss ,
scndry_vect_out => open
);
gtrxreset_in_cdc_sync : east_channel_cdc_sync
generic map
(
c_cdc_type => 1 ,
c_flop_input => 1 ,
c_reset_state => 0 ,
c_single_bit => 1 ,
c_vector_width => 2 ,
c_mtbf_stages => 6
)
port map
(
prmry_aclk => STABLE_CLOCK ,
prmry_resetn => '1' ,
prmry_in => GTRXRESET_IN ,
prmry_vect_in => "00" ,
scndry_aclk => DRPCLK ,
scndry_resetn => '1' ,
prmry_ack => open ,
scndry_out => gtrxreset_f ,
scndry_vect_out => open
);
--output assignment
GTRXRESET_OUT <= gtrxreset_o;
DRPEN <= drpen_o;
DRPWE <= drpwe_o;
DRPADDR <= drpaddr_o;
DRPDI <= drpdi_o;
DRP_OP_DONE <= drp_op_done_o;
PROCESS (DRPCLK, rst_ss)
BEGIN
IF (rst_ss = '1') THEN
state <= idle after DLY;
gtrxreset_s <= '0' after DLY;
gtrxreset_ss <= '0' after DLY;
rxpmaresetdone_sss <= '0' after DLY;
rd_data <= x"0000" after DLY;
gtrxreset_o <= '0' after DLY;
ELSIF (DRPCLK'event and DRPCLK='1') THEN
state <= next_state after DLY;
gtrxreset_s <= gtrxreset_f after DLY;
gtrxreset_ss <= gtrxreset_s after DLY;
rxpmaresetdone_sss <= rxpmaresetdone_ss after DLY;
rd_data <= next_rd_data after DLY;
gtrxreset_o <= gtrxreset_i after DLY;
END IF;
END PROCESS;
PROCESS (DRPCLK, gtrxreset_f)
BEGIN
IF (gtrxreset_f = '1') THEN
drp_op_done_o <= '0' after DLY;
ELSIF (DRPCLK'event and DRPCLK='1') THEN
IF (state = wait_wr_done2 and DRPRDY = '1') THEN
drp_op_done_o <= '1' after DLY;
ELSE
drp_op_done_o <= drp_op_done_o after DLY;
END IF;
END IF;
END PROCESS;
pmarstdone_fall_edge <= (not rxpmaresetdone_ss) and (rxpmaresetdone_sss);
PROCESS (gtrxreset_ss,DRPRDY,state,pmarstdone_fall_edge)
BEGIN
CASE state IS
WHEN idle =>
IF (gtrxreset_ss='1') THEN
next_state <= drp_rd;
ELSE
next_state <= idle;
END IF;
WHEN drp_rd =>
next_state<= wait_rd_data;
WHEN wait_rd_data =>
IF (DRPRDY='1')THEN
next_state <= wr_16;
ELSE
next_state <= wait_rd_data;
END IF;
WHEN wr_16 =>
next_state <= wait_wr_done1;
WHEN wait_wr_done1 =>
IF (DRPRDY='1') THEN
next_state <= wait_pmareset;
ELSE
next_state <= wait_wr_done1;
END IF;
WHEN wait_pmareset =>
IF (pmarstdone_fall_edge='1') THEN
next_state <= wr_20;
ELSE
next_state <= wait_pmareset;
END IF;
WHEN wr_20 =>
next_state <= wait_wr_done2;
WHEN wait_wr_done2 =>
IF (DRPRDY='1') THEN
next_state <= idle;
ELSE
next_state <= wait_wr_done2;
END IF;
WHEN others=>
next_state <= idle;
END CASE;
END PROCESS;
-- drives DRP interface and GTRXRESET_OUT
PROCESS(DRPRDY,state,rd_data,DRPDO,gtrxreset_ss,flag,original_rd_data)
BEGIN
-- assert gtrxreset_out until wr to 16-bit is complete
-- RX_DATA_WIDTH is located at addr x"0011", [13 downto 11]
-- encoding is this : /16 = x "2", /20 = x"3", /32 = x"4", /40 = x"5"
gtrxreset_i <= '0';
drpaddr_o <= '0'& x"11"; -- 000010001
drpen_o <= '0';
drpwe_o <= '0';
drpdi_o <= x"0000";
next_rd_data <= rd_data;
CASE state IS
--do nothing to DRP or reset
WHEN idle => null;
--assert reset and issue rd
WHEN drp_rd =>
gtrxreset_i <= '1';
drpen_o <= '1';
drpwe_o <= '0';
--assert reset and wait to load rd data
WHEN wait_rd_data =>
gtrxreset_i <= '1';
IF (DRPRDY = '1' and flag = '0') THEN
next_rd_data <= DRPDO;
ELSIF (DRPRDY = '1' and flag = '1') THEN
next_rd_data <= original_rd_data;
ELSE
next_rd_data <= rd_data;
END IF;
--assert reset and write to 16-bit mode
WHEN wr_16=>
gtrxreset_i<= '1';
drpen_o <= '1';
drpwe_o <= '1';
-- Addr "00001001" [11] = '0' puts width mode in /16 or /32
drpdi_o <= rd_data(15 downto 12) & '0' & rd_data(10 downto 0);
--keep asserting reset until write to 16-bit mode is complete
WHEN wait_wr_done1=>
gtrxreset_i <= '1';
--deassert reset and no DRP access until 2nd pmareset
WHEN wait_pmareset => null;
IF (gtrxreset_ss='1') THEN
gtrxreset_i <= '1';
ELSE
gtrxreset_i <= '0';
END IF;
--write to 20-bit mode
WHEN wr_20 =>
drpen_o <='1';
drpwe_o <= '1';
drpdi_o <= rd_data(15 downto 0); --restore user setting per prev read
--wait to complete write to 20-bit mode
WHEN wait_wr_done2 => null;
WHEN others => null;
END CASE;
END PROCESS;
END Behavioral;
ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_aurora_pkg.vhd deleted 100644 → 0
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-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--
-- AURORA
--
--
-- Description: Aurora Package Definition
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
package AURORA_PKG is
function std_bool (EXP_IN : in boolean) return std_logic;
end;
package body AURORA_PKG is
function std_bool (EXP_IN : in boolean) return std_logic is
begin
if (EXP_IN) then
return('1');
else
return('0');
end if;
end std_bool;
end;
ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_axi_to_ll.vhd deleted 100644 → 0
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------------------------------------------------------------------------------
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
------------------------------------------------------------------------------
--
-- AXI_TO_LL
--
--
-- Description: This light wrapper/shim convertes Legacy LocalLink interface
-- signals from AXI-4 Stream protocol signals
--
--
------------------------------------------------------------------------------/
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_MISC.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity east_channel_AXI_TO_LL is
generic
(
DATA_WIDTH : integer := 16; -- DATA bus width
STRB_WIDTH : integer := 2; -- STROBE bus width
REM_WIDTH : integer := 1; -- REM bus width
USE_4_NFC : integer := 0; -- 0 => PDU, 1 => NFC, 2 => UFC
USE_UFC_REM : integer := 0 -- UFC REM bus width identifier
);
port
(
---------------------- AXI4-S Interface -------------------------------
AXI4_S_IP_TX_TDATA : in std_logic_vector (0 to DATA_WIDTH-1);
AXI4_S_IP_TX_TKEEP : in std_logic_vector (0 to STRB_WIDTH-1);
AXI4_S_IP_TX_TVALID : in std_logic;
AXI4_S_IP_TX_TLAST : in std_logic;
AXI4_S_OP_TX_TREADY : out std_logic;
---------------------- LocalLink Interface ----------------------------
LL_OP_DATA : out std_logic_vector (0 to DATA_WIDTH-1);
LL_OP_REM : out std_logic_vector (0 to REM_WIDTH -1);
LL_OP_SRC_RDY_N : out std_logic;
LL_OP_SOF_N : out std_logic;
LL_OP_EOF_N : out std_logic;
LL_IP_DST_RDY_N : in std_logic;
---------------------- System Interface ----------------------------
USER_CLK : in std_logic;
RESET : in std_logic;
CHANNEL_UP : in std_logic
);
end east_channel_AXI_TO_LL;
architecture BEHAVIORAL of east_channel_AXI_TO_LL is
attribute core_generation_info : string;
attribute core_generation_info of BEHAVIORAL : architecture is "east_channel,aurora_8b10b_v11_1_8,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=1,c_column_used=None,c_gt_clock_1=GTPQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=1,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=50000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=Duplex}";
--***********************************Parameter Declarations***************************
constant DLY : time := 1 ns;
signal new_pkt_r : std_logic;
signal new_pkt : std_logic;
signal temp_cond : std_logic;
signal ll_op_sof : std_logic;
signal ll_ip_dst_rdy : std_logic;
signal AXI4_S_IP_TX_TKEEP_i : std_logic_vector(0 to STRB_WIDTH-1);
begin
--*********************************Main Body of Code**********************************
ll_ip_dst_rdy <= not LL_IP_DST_RDY_N;
LL_OP_DATA <= AXI4_S_IP_TX_TDATA;
AXI4_S_IP_TX_TKEEP_i <= AXI4_S_IP_TX_TKEEP;
LL_OP_SRC_RDY_N <= not AXI4_S_IP_TX_TVALID;
LL_OP_EOF_N <= not AXI4_S_IP_TX_TLAST;
LL_OP_REM <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3)) - '1';
new_pkt <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
'1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else
new_pkt_r;
temp_cond <= '0' when (new_pkt_r = '1') else
'1';
ll_op_sof <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
(new_pkt and (not new_pkt_r));
LL_OP_SOF_N <= not ll_op_sof;
process(USER_CLK)
begin
if(USER_CLK'event and USER_CLK='1') then
if(RESET = '1') then
new_pkt_r <= '0' after DLY;
elsif(CHANNEL_UP = '1') then
new_pkt_r <= new_pkt after DLY;
else
new_pkt_r <= '0' after DLY;
end if;
end if;
end process;
-- Assign output from temp signal
AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy;
end BEHAVIORAL;
ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_channel_err_detect.vhd deleted 100644 → 0
+ 0
− 202
View file @ 13c6a086
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--
-- CHANNEL_ERR_DETECT
--
--
-- Description: the CHANNEL_ERR_DETECT module monitors the error signals
-- from the Aurora Lanes in the channel. If one or more errors
-- are detected, the error is reported as a channel error. If
-- a hard error is detected, it sends a message to the channel
-- initialization state machine to reset the channel.
--
-- This module supports 1 4-byte lane designs
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity east_channel_CHANNEL_ERR_DETECT is
port (
-- Aurora Lane Interface
SOFT_ERR : in std_logic_vector(0 to 1);
HARD_ERR : in std_logic;
LANE_UP : in std_logic;
-- System Interface
USER_CLK : in std_logic;
POWER_DOWN : in std_logic;
CHANNEL_SOFT_ERR : out std_logic;
CHANNEL_HARD_ERR : out std_logic;
-- Channel Init SM Interface
RESET_CHANNEL : out std_logic
);
end east_channel_CHANNEL_ERR_DETECT;
architecture RTL of east_channel_CHANNEL_ERR_DETECT is
-- Parameter Declarations --
constant DLY : time := 1 ns;
-- External Register Declarations --
signal CHANNEL_SOFT_ERR_Buffer : std_logic := '1';
signal CHANNEL_HARD_ERR_Buffer : std_logic := '1';
signal RESET_CHANNEL_Buffer : std_logic := '1';
-- Internal Register Declarations --
signal soft_err_r : std_logic_vector(0 to 1);
signal hard_err_r : std_logic;
signal lane_up_r : std_logic;
-- Wire Declarations --
signal channel_soft_err_c : std_logic;
signal channel_hard_err_c : std_logic;
signal reset_channel_c : std_logic;
begin
CHANNEL_SOFT_ERR <= CHANNEL_SOFT_ERR_Buffer;
CHANNEL_HARD_ERR <= CHANNEL_HARD_ERR_Buffer;
RESET_CHANNEL <= RESET_CHANNEL_Buffer;
-- Main Body of Code --
-- Register all of the incoming error signals. This is neccessary for timing.
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
soft_err_r <= SOFT_ERR after DLY;
hard_err_r <= HARD_ERR after DLY;
end if;
end process;
-- Assert Channel soft error if any of the soft error signals are asserted.
channel_soft_err_c <= soft_err_r(0) or
soft_err_r(1);
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_SOFT_ERR_Buffer <= channel_soft_err_c after DLY;
end if;
end process;
-- Assert Channel hard error if any of the hard error signals are asserted.
channel_hard_err_c <= hard_err_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
CHANNEL_HARD_ERR_Buffer <= channel_hard_err_c after DLY;
end if;
end process;
-- FF stage added for timing closure
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
lane_up_r <= LANE_UP after DLY;
end if;
end process;
-- "reset_channel_c" is asserted when any of the LANE_UP signals are low.
reset_channel_c <= not lane_up_r;
process (USER_CLK)
begin
if (USER_CLK 'event and USER_CLK = '1') then
RESET_CHANNEL_Buffer <= reset_channel_c or POWER_DOWN after DLY;
end if;
end process;
end RTL;
ips/hw/scalp_aurora_phy/src/ip_core/east_channel/east_channel/src/east_channel_chbond_count_dec_4byte.vhd deleted 100644 → 0
+ 0
− 105
View file @ 13c6a086
-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--
-- CHBOND_COUNT_DEC_4BYTE
--
--
--
-- Description: This module decodes the GTX's RXSTATUS signals. RXSTATUS[5] indicates
-- that Channel Bonding is complete
--
-- * Supports Virtex-5
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.AURORA_PKG.all;
entity east_channel_CHBOND_COUNT_DEC_4BYTE is
port (
RX_STATUS : in std_logic_vector(5 downto 0);
CHANNEL_BOND_LOAD : out std_logic;
USER_CLK : in std_logic
);
end east_channel_CHBOND_COUNT_DEC_4BYTE;
architecture RTL of east_channel_CHBOND_COUNT_DEC_4BYTE is
-- Parameter Declarations --
constant DLY : time := 1 ns;
constant CHANNEL_BOND_LOAD_CODE : std_logic_vector(5 downto 0) := "100111"; -- Status bus code: Channel Bond load complete
-- External Register Declarations
signal CHANNEL_BOND_LOAD_Buffer : std_logic;
begin
CHANNEL_BOND_LOAD <= CHANNEL_BOND_LOAD_Buffer;
-- Main Body of Code --
process (USER_CLK)
begin
if (USER_CLK'event and USER_CLK = '1') then
CHANNEL_BOND_LOAD_Buffer <= std_bool(RX_STATUS = CHANNEL_BOND_LOAD_CODE) after DLY;
end if;
end process;
end RTL;
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