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Commit 0836c0c9 authored by joachim.schmidt's avatar joachim.schmidt
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updated Scalp Router for debugging

parent f9b74c88
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......@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
......@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
-- Last update: 2021-01-11
-- Last update: 2021-05-05
--
---------------------------------------------------------------------------------
......@@ -525,36 +525,46 @@ architecture arch of scalp_firmware is
attribute keep of GTRefClk1xC : signal is "true";
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- North
-- East
-- attribute mark_debug of EastRXM2SxD : signal is "true";
-- attribute keep of EastRXM2SxD : signal is "true";
-- attribute mark_debug of EastRXS2MxD : signal is "true";
-- attribute keep of EastRXS2MxD : signal is "true";
-- attribute mark_debug of EastTXM2SxD : signal is "true";
-- attribute keep of EastTXM2SxD : signal is "true";
-- attribute mark_debug of EastTXS2MxD : signal is "true";
-- attribute keep of EastTXS2MxD : signal is "true";
-- South
-- West
-- attribute mark_debug of WestRXM2SxD : signal is "true";
-- attribute keep of WestRXM2SxD : signal is "true";
-- attribute mark_debug of WestRXS2MxD : signal is "true";
-- attribute keep of WestRXS2MxD : signal is "true";
-- attribute mark_debug of WestTXM2SxD : signal is "true";
-- attribute keep of WestTXM2SxD : signal is "true";
-- attribute mark_debug of WestTXS2MxD : signal is "true";
-- attribute keep of WestTXS2MxD : signal is "true";
-- attribute mark_debug of ScalpRouterReadyxD : signal is "true";
-- attribute keep of ScalpRouterReadyxD : signal is "true";
-- Scalp Router
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-- attribute keep of RXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
-- attribute keep of RXAxiss2mVectorxD : signal is "true";
-- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
-- attribute keep of TXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
-- attribute keep of TXAxiss2mVectorxD : signal is "true";
-- Scalp Aurora PHY Ready -> TX Side
attribute mark_debug of NorthTXM2SxD : signal is "true";
attribute keep of NorthTXM2SxD : signal is "true";
attribute mark_debug of NorthTXS2MxD : signal is "true";
attribute keep of NorthTXS2MxD : signal is "true";
attribute mark_debug of EastTXM2SxD : signal is "true";
attribute keep of EastTXM2SxD : signal is "true";
attribute mark_debug of EastTXS2MxD : signal is "true";
attribute keep of EastTXS2MxD : signal is "true";
attribute mark_debug of SouthTXM2SxD : signal is "true";
attribute keep of SouthTXM2SxD : signal is "true";
attribute mark_debug of SouthTXS2MxD : signal is "true";
attribute keep of SouthTXS2MxD : signal is "true";
attribute mark_debug of WestTXM2SxD : signal is "true";
attribute keep of WestTXM2SxD : signal is "true";
attribute mark_debug of WestTXS2MxD : signal is "true";
attribute keep of WestTXS2MxD : signal is "true";
attribute mark_debug of NorthRXM2SxD : signal is "true";
attribute keep of NorthRXM2SxD : signal is "true";
attribute mark_debug of NorthRXS2MxD : signal is "true";
attribute keep of NorthRXS2MxD : signal is "true";
attribute mark_debug of EastRXM2SxD : signal is "true";
attribute keep of EastRXM2SxD : signal is "true";
attribute mark_debug of EastRXS2MxD : signal is "true";
attribute keep of EastRXS2MxD : signal is "true";
attribute mark_debug of SouthRXM2SxD : signal is "true";
attribute keep of SouthRXM2SxD : signal is "true";
attribute mark_debug of SouthRXS2MxD : signal is "true";
attribute keep of SouthRXS2MxD : signal is "true";
attribute mark_debug of WestRXM2SxD : signal is "true";
attribute keep of WestRXM2SxD : signal is "true";
attribute mark_debug of WestRXS2MxD : signal is "true";
attribute keep of WestRXS2MxD : signal is "true";
begin
......@@ -901,7 +911,14 @@ begin
signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE;
signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE;
signal VioWrSpValidxS : std_ulogic := '0';
-- Scalp Packet
attribute mark_debug of ScalpPacket0xD : signal is "true";
attribute keep of ScalpPacket0xD : signal is "true";
attribute mark_debug of ScalpPacketValid12xS : signal is "true";
attribute keep of ScalpPacketValid12xS : signal is "true";
-- VIO
-- attribute mark_debug of VioWrSpValidxS : signal is "true";
-- attribute keep of VioWrSpValidxS : signal is "true";
-- attribute mark_debug of ScalpRouterResetxRNA : signal is "true";
-- attribute keep of ScalpRouterResetxRNA : signal is "true";
-- attribute mark_debug of ScalpPacket0xD : signal is "true";
......
......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router (NoC).
--
-- Last update: 2020-12-21
-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
......@@ -148,6 +148,8 @@ architecture rtl of scalp_router is
attribute mark_debug : string;
attribute keep : string;
--
-- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
-- attribute keep of TXAxiss2mVectorxD : signal is "true";
-- attribute mark_debug of LocNetAddrxD : signal is "true";
-- attribute keep of LocNetAddrxD : signal is "true";
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
......
......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Interface.
--
-- Last update: 2020-11-30
-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
......@@ -216,6 +216,23 @@ architecture rtl of scalp_router_interface is
signal DTXAxi4M2SLinkxD : t_axi4m2s := C_NO_AXI4_M2S;
signal DTXAxi4S2MLinkxD : t_axi4s2m := C_NO_AXI4_S2M;
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
-- attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
-- attribute keep of TXAxi4S2MLinkxD : signal is "true";
-- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
-- attribute keep of TXAxi4s2mLinksxD : signal is "true";
-- attribute mark_debug of TXAxi4s2mIfxD : signal is "true";
-- attribute keep of TXAxi4s2mIfxD : signal is "true";
-- attribute mark_debug of RXAxi4s2mIfxD : signal is "true";
-- attribute keep of RXAxi4s2mIfxD : signal is "true";
-- attribute mark_debug of TXAxi4s2mLinksxD : signal is "true";
-- attribute keep of TXAxi4s2mLinksxD : signal is "true";
-- attribute mark_debug of RXAxi4s2mLinksxD : signal is "true";
-- attribute keep of RXAxi4s2mLinksxD : signal is "true";
begin -- architecture rtl
EntityIOxB : block is
......
......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp RX side state machine.
--
-- Last update: 2020-11-30
-- Last update: 2021-05-05
--
---------------------------------------------------------------------------------
library ieee;
......@@ -115,6 +115,37 @@ architecture behavioral of scalp_rx_side is
signal ReadyOutxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EnPopNPushxS : std_ulogic := '0';
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
attribute mark_debug of TXAxi4S2MLinkxD : signal is "true";
attribute keep of TXAxi4S2MLinkxD : signal is "true";
attribute mark_debug of RXSideStatexDP : signal is "true";
attribute keep of RXSideStatexDP : signal is "true";
attribute mark_debug of RXSideStatexDN : signal is "true";
attribute keep of RXSideStatexDN : signal is "true";
attribute mark_debug of ReadyInxD : signal is "true";
attribute keep of ReadyInxD : signal is "true";
attribute mark_debug of ReadyOutxD : signal is "true";
attribute keep of ReadyOutxD : signal is "true";
attribute mark_debug of ArbitratexS : signal is "true";
attribute keep of ArbitratexS : signal is "true";
attribute mark_debug of RequestVectorxDP : signal is "true";
attribute keep of RequestVectorxDP : signal is "true";
attribute mark_debug of ArbitratedxS : signal is "true";
attribute keep of ArbitratedxS : signal is "true";
attribute mark_debug of GrantIndexxD : signal is "true";
attribute keep of GrantIndexxD : signal is "true";
attribute mark_debug of RequestVectorxDN : signal is "true";
attribute keep of RequestVectorxDN : signal is "true";
attribute mark_debug of SchedulerAckxD : signal is "true";
attribute keep of SchedulerAckxD : signal is "true";
attribute mark_debug of RXAxi4S2MLinkxD : signal is "true";
attribute keep of RXAxi4S2MLinkxD : signal is "true";
attribute mark_debug of RXAxi4M2SLinkxD : signal is "true";
attribute keep of RXAxi4M2SLinkxD : signal is "true";
begin -- architecture behavioral
-- Asynchronous Statements
......
......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp TX side state machine.
--
-- Last update: 2020-11-30
-- Last update: 2021-05-04
--
---------------------------------------------------------------------------------
library ieee;
......@@ -90,6 +90,16 @@ architecture behavioral of scalp_tx_side is
signal ReadyInxD : t_axi4s2m := C_NO_AXI4_S2M;
signal EnPopNPushxS : std_ulogic := '0';
attribute mark_debug : string;
attribute keep : string;
--
-- attribute mark_debug of TXSideStatexDP : signal is "true";
-- attribute keep of TXSideStatexDP : signal is "true";
-- attribute mark_debug of TXSideStatexDN : signal is "true";
-- attribute keep of TXSideStatexDN : signal is "true";
-- attribute mark_debug of ReadyInxD : signal is "true";
-- attribute keep of ReadyInxD : signal is "true";
begin -- architecture behavioral
-- Asynchronous Statements
......
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_zynqps_wrapper
--
-- Last update: 2021-03-22
-- Last update: 2021-05-03
--
---------------------------------------------------------------------------------
......@@ -66,8 +66,7 @@ entity scalp_zynqps_wrapper is
RdValidxSO : out std_logic;
WrAddrxDO : out std_logic_vector (11 downto 0);
WrDataxDO : out std_logic_vector (31 downto 0);
WrValidxSO : out std_logic;
RgbLedsCtrlPortxDO : out std_logic_vector (31 downto 0));
WrValidxSO : out std_logic);
end scalp_zynqps_wrapper;
......@@ -110,7 +109,6 @@ begin
RdValidxSO => RdValidxSO,
WrAddrxDO => WrAddrxDO,
WrDataxDO => WrDataxDO,
WrValidxSO => WrValidxSO,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxDO);
WrValidxSO => WrValidxSO);
end arch;
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