Commit 183400d8 authored by joachim.schmidt's avatar joachim.schmidt
Browse files

Updated scalp_fast_router_firmware. Support DMA sync between two scalp_board.

parent 8d507bb7
......@@ -64,7 +64,9 @@ entity scalp_fast_router_registers is
DMAFifoRXWrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXRrDataCntxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
DMAFifoRXStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
QoSPhyStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSDMAInitOcpCtrlxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0);
QoSDMAInitStatusxDI : in std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
end scalp_fast_router_registers;
......@@ -82,49 +84,74 @@ architecture behavioral of scalp_fast_router_registers is
-- Signals
-- Clock and reset
signal SAxiClkxC : std_ulogic := '0';
signal SAxiRstxRAN : std_ulogic := '0';
signal SAxiClkxC : std_ulogic := '0';
signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
signal SAxiARReadyxS : std_ulogic := '0';
signal SAxiRValidxS : std_ulogic := '0';
signal SAxiBValidxS : std_ulogic := '0';
signal SAxiWReadyxS : std_ulogic := '0';
signal SAxiAWReadyxS : std_ulogic := '0';
signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal SAxiARReadyxS : std_ulogic := '0';
signal SAxiRValidxS : std_ulogic := '0';
signal SAxiBValidxS : std_ulogic := '0';
signal SAxiWReadyxS : std_ulogic := '0';
signal SAxiAWReadyxS : std_ulogic := '0';
signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RdValidxS : std_ulogic := '0';
signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal WrValidxS : std_ulogic := '0';
signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RdValidxS : std_ulogic := '0';
signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal WrValidxS : std_ulogic := '0';
-- Registers list
signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal LocalNetAddrPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal LocalNetAddrPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed0PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RGBLed1PortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoTXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXWrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXRrDataCntPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal DMAFifoRXStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSPhyStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitOcpCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitOcpCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitStatusPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal QoSDMAInitStatusPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
-- Debug
signal WValidxS : std_ulogic := '0';
signal AWValidxS : std_ulogic := '0';
signal WDataxD : std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0) := (others => '0');
signal AWAddrxD : std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0) := (others => '0');
-- Attributes
attribute mark_debug : string;
attribute keep : string;
attribute mark_debug : string;
attribute keep : string;
--
attribute mark_debug of WrValidxS : signal is "true";
attribute keep of WrValidxS : signal is "true";
attribute mark_debug of WrAddrxD : signal is "true";
attribute keep of WrAddrxD : signal is "true";
attribute mark_debug of WrDataxD : signal is "true";
attribute keep of WrDataxD : signal is "true";
attribute mark_debug of WValidxS : signal is "true";
attribute keep of WValidxS : signal is "true";
attribute mark_debug of AWValidxS : signal is "true";
attribute keep of AWValidxS : signal is "true";
attribute mark_debug of WDataxD : signal is "true";
attribute keep of WDataxD : signal is "true";
attribute mark_debug of AWAddrxD : signal is "true";
attribute keep of AWAddrxD : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
......@@ -160,7 +187,7 @@ begin
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
WrValidxAS : WrValidxS <= SAxiWValidxSI;
WrValidxAS : WrValidxS <= SAxiWValidxSI and not SAxiAWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
......@@ -169,6 +196,16 @@ begin
end block EntityIOxB;
DebugxB : block is
begin -- block DebugxB
WValidxAS : WValidxS <= SAxiWValidxSI;
AWValidxAS : AWValidxS <= SAxiAWValidxSI;
WDataxAS : WDataxD <= SAxiWDataxDI;
AWAddrxAS : AWAddrxD <= SAxiAWAddrxDI;
end block DebugxB;
AXI4LitexB : block is
begin -- block AXI4LitexB
......@@ -302,7 +339,9 @@ begin
WriteRegPortxP : process (DMAFifoRXRrDataCntxDI, DMAFifoRXStatusxDI,
DMAFifoRXWrDataCntxDI, DMAFifoTXRrDataCntxDI,
DMAFifoTXStatusxDI, DMAFifoTXWrDataCntxDI,
LocalNetAddrPortxDP, QoSPhyStatusxDI,
LocalNetAddrPortxDP,
QoSDMAInitOcpCtrlPortxDP,
QoSDMAInitStatusxDI, QoSPhyStatusxDI,
RGBLed0PortxDP, RGBLed1PortxDP, WrAddrxD,
WrDataxD, WrValidxS) is
begin -- process WriteRegPortxP
......@@ -319,12 +358,16 @@ begin
DMAFifoRXRrDataCntPortxDN <= DMAFifoRXRrDataCntxDI;
DMAFifoRXStatusPortxDN <= DMAFifoRXStatusxDI;
QoSPhyStatusPortxDN <= QoSPhyStatusxDI;
QoSDMAInitOcpCtrlPortxDN <= (others => '0');
QoSDMAInitOcpCtrlxDO <= QoSDMAInitOcpCtrlPortxDP;
QoSDMAInitStatusPortxDN <= QoSDMAInitStatusxDI;
if WrValidxS = '1' then
case WrAddrxD is
when x"000" => LocalNetAddrPortxDN <= WrDataxD;
when x"004" => RGBLed0PortxDN <= WrDataxD;
when x"008" => RGBLed1PortxDN <= WrDataxD;
when x"000" => LocalNetAddrPortxDN <= WrDataxD;
when x"004" => RGBLed0PortxDN <= WrDataxD;
when x"008" => RGBLed1PortxDN <= WrDataxD;
when x"028" => QoSDMAInitOcpCtrlPortxDN <= WrDataxD;
when others => null;
end case;
......@@ -350,6 +393,7 @@ begin
when x"01C" => RdDataxD <= DMAFifoRXRrDataCntPortxDP;
when x"020" => RdDataxD <= DMAFifoRXStatusPortxDP;
when x"024" => RdDataxD <= QoSPhyStatusPortxDP;
when x"02C" => RdDataxD <= QoSDMAInitStatusPortxDP;
when others => RdDataxD <= (others => '0');
end case;
......@@ -370,6 +414,8 @@ begin
DMAFifoRXRrDataCntPortxDP <= x"00000000";
DMAFifoRXStatusPortxDP <= x"00000000";
QoSPhyStatusPortxDP <= x"00000000";
QoSDMAInitOcpCtrlPortxDP <= x"00000000";
QoSDMAInitStatusPortxDP <= x"00000000";
elsif rising_edge(SAxiClkxC) then
LocalNetAddrPortxDP <= LocalNetAddrPortxDN;
......@@ -382,6 +428,8 @@ begin
DMAFifoRXRrDataCntPortxDP <= DMAFifoRXRrDataCntPortxDN;
DMAFifoRXStatusPortxDP <= DMAFifoRXStatusPortxDN;
QoSPhyStatusPortxDP <= QoSPhyStatusPortxDN;
QoSDMAInitOcpCtrlPortxDP <= QoSDMAInitOcpCtrlPortxDN;
QoSDMAInitStatusPortxDP <= QoSDMAInitStatusPortxDN;
end if;
end process UpdateRegBankxP;
......
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: Box for dropping packets.
--
-- Last update: 2021-10-22
-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
library ieee;
......@@ -40,6 +40,8 @@ entity scalp_dropbox is
-- System Clock and Reset
SysClkxCI : in std_ulogic;
SysRstxRNAI : in std_ulogic;
-- Source Interfaces Number
IfSrcNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
-- Destination Interface Number
IfDstNumxDI : in integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSI : in std_ulogic;
......@@ -48,6 +50,7 @@ entity scalp_dropbox is
-- QoS Vector
QoSVectorPhyStatusxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);
-- Dropped signals
ToBeDroppedxSI : in std_ulogic;
ToBeDroppedxSO : out std_ulogic;
IsDroppedxSI : in std_ulogic);
......@@ -64,11 +67,13 @@ architecture behavioral of scalp_dropbox is
constant C_SCALP_BOTTOM_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 5;
constant C_SCALP_LOCAL_NUM : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 6;
signal IfSrcNumInxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfDstNumInxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidInxS : std_ulogic := '0';
signal IfDstNumOutxD : integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1) := 0;
signal IfNumValidOutxS : std_ulogic := '0';
signal QoSVectorPhyStatusxD : t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0) := (others => C_SCALP_NO_QOS);
signal ToBeDroppedFromRCxS : std_ulogic := '0';
signal ToBeDroppedxS : std_ulogic := '0';
signal IsDroppedxS : std_ulogic := '0';
......@@ -81,12 +86,14 @@ begin -- architecture behavioral
EntityIOxB : block is
begin -- block EntityIOxB
IfSrcNumInxAS : IfSrcNumInxD <= IfSrcNumxDI;
IfDstNumInxAS : IfDstNumInxD <= IfDstNumxDI;
IfNumValidInxAS : IfNumValidInxS <= IfNumValidxSI;
IfDstNumOutxAS : IfDstNumxDO <= IfDstNumOutxD;
IfNumValidOutxAS : IfNumValidxSO <= IfNumValidOutxS;
QoSVectorPhyStatusxAS : QoSVectorPhyStatusxD <= QoSVectorPhyStatusxDI;
ToBeDroppedxAS : ToBeDroppedxSO <= ToBeDroppedxS;
ToBeDroppedFromRCxAS : ToBeDroppedFromRCxS <= ToBeDroppedxSI;
IsDroppedxAS : IsDroppedxS <= IsDroppedxSI;
end block EntityIOxB;
......@@ -101,7 +108,8 @@ begin -- architecture behavioral
IfNumValidOutxS <= '0';
IfDstNumOutxD <= C_SCALP_NO_NUM;
if (IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 0) then
if ((IfNumValidInxS = '1') and (to_integer(QoSVectorPhyStatusxD(IfDstNumInxD)) = 0)) or
(ToBeDroppedFromRCxS = '1') then
ToBeDroppedxS <= '1';
IfDstNumOutxD <= C_SCALP_NO_NUM;
IfNumValidOutxS <= '0';
......
......@@ -15,7 +15,7 @@
-- Tool version: 2019.1
-- Description: Scalp Router Core Algorithm
--
-- Last update: 2021-10-22
-- Last update: 2021-10-26
--
---------------------------------------------------------------------------------
library ieee;
......@@ -52,7 +52,9 @@ entity scalp_router_core is
IfDstNumxDO : out integer range 0 to (C_SCALP_INTERFACE_VECTOR_SIZE - 1);
IfNumValidxSO : out std_ulogic;
-- QoS Vector
QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0));
QoSVectorxDI : in t_scalp_qos_vector((C_SCALP_INTERFACE_VECTOR_SIZE - 1) downto 0);