Updated scalp_safe_firmware with new SoC block design

designs/vivado/scalp_safe_firmware/2020.2/lin64/.gitignore

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_safe_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Git ignore file
+#
+# Last update: 2021-10-14 11:46:11
+#
+##################################################################################
+
+# Ignore generated project directory
+scalp_safe_firmware
+.scripts/scalp_zynqps_safe
+.scripts/.Xil
\ No newline at end of file

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl

@@ -15,23 +15,33 @@
 # Tool version: 2020.2
 # Description: Console color print utility
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 
+# Try to set a variable with an execution command
+# If the command fails, set the variable to an empty string
+# cmd - The command to be executed
+# return The variable to be set
+proc try_setexec {cmd} {
+  set code [catch { set var [exec {*}$cmd] } ]
+  if { $code != 0 } { set var "" }
+
+  return ${var}
+}
+
 # Text attributes
-set RESET [exec tput sgr0]
-set BOLD [exec tput bold]
-set ITALIC [exec tput sitm]
-set BLINK [exec tput blink]
-set HIGHL [exec tput smso]
+set RESET [try_setexec "tput sgr0"]
+set BOLD [try_setexec "tput bold"]
+set ITALIC [try_setexec "tput sitm"]
+set BLINK [try_setexec "tput blink"]
+set HIGHL [try_setexec "tput smso"]
 
 # Text colors
-set RED [exec tput setaf 1]
-set GREEN [exec tput setaf 2]
-set YELLOW [exec tput setaf 3]
-set BLUE [exec tput setaf 4]
-set MAGENTA [exec tput setaf 5]
-set CYAN [exec tput setaf 6]
-set WHITE [exec tput setaf 7]
-
+set RED [try_setexec "tput setaf 1"]
+set GREEN [try_setexec "tput setaf 2"]
+set YELLOW [try_setexec "tput setaf 3"]
+set BLUE [try_setexec "tput setaf 4"]
+set MAGENTA [try_setexec "tput setaf 5"]
+set CYAN [try_setexec "tput setaf 6"]
+set WHITE [try_setexec "tput setaf 7"]

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/clean_prj_scalp_safe_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Cleanup project directory
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 
@@ -31,10 +31,5 @@ rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
 # Remove generated project directory
 rm -rf ${PRJ_DIR}/scalp_safe_firmware/ 2> /dev/null
 
-# Clean app directory
-rm ${PRJ_DIR}/app/*.h 2> /dev/null
-rm ${PRJ_DIR}/app/*.c 2> /dev/null
-rm ${PRJ_DIR}/app/*.html 2> /dev/null
-
 echo "> Done"
 

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware.sh

@@ -17,7 +17,7 @@
 # Tool version: 2020.2
 # Description: Create Vivado project
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/create_prj_scalp_safe_firmware.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script for re-creating Vivado project 'scalp_safe_firmware'
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 
@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
 # Set the original project directory path for adding/importing sources in the new project
 set src_dir "${PRJ_DIR}/../src"
 set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
 set comp_dir "${ip_dir}/$prj_name"
 set comp_src_dir "${comp_dir}/src"
 set pkg_src_dir "${PKG_DIR}/hw"
@@ -49,56 +50,64 @@ set_property target_language VHDL [current_project]
 print_status "Create project" "OK"
 
 # Map the IP Repository so that custom IP is included
-set_property ip_repo_paths $ip_dir [current_fileset]
+set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
 update_ip_catalog
 
 #----------------------------------------------------------------
 # Add project sources
 #----------------------------------------------------------------
 
+# Get HDL source files directory
 if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	# add HDL sources
-	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
-	add_files -norecurse $hdl_src_file_list    
-	# add the constraints file (XDC)
-	add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_safe_firmware.xdc
+    set hdl_src_dir "${src_dir}/hdl"
+    set sim_src_dir "${src_dir}/sim"
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+    # components sources are stored in an external directory
+    set hdl_src_dir "${comp_src_dir}/hdl"
+    set sim_src_dir "${comp_src_dir}/sim"
+}    
+
+# add HDL source files
+set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
+set verilog_src_file_list [findFiles $hdl_src_dir *.v]
+set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
+set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
+
+if {$hdl_src_file_list != ""} {
+  add_files -norecurse $hdl_src_file_list
+} else {
+  print_status "No sources to be added" "WARNING"
+}
+
+# Set VHDL version
+foreach j $vhdl_src_file_list {
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+# Add constraint files and IPs source files
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {  
+  # add the constraints file (XDC)
+  add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_safe_firmware.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/scalp_safe_firmware.xdc]
-add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
-add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
 	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
-add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
-
-	# add IPs source file
+	
+  # add IPs source files
   
 } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	# components sources are stored in an external directory
-	# add the project component
-	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
-	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
-	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
-	add_files -norecurse $hdl_src_file_list
-	# add IPs source file
+  # add IPs source files
   
-	# add IP-XACT source file
-	#add_files -norecurse $comp_dir/component.xml
+  # add IP-XACT source file
+  #add_files -norecurse $comp_dir/component.xml
 }
 print_status "Add project sources" "OK"
 
-foreach j $vhdl_src_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
-}
-print_status "VHDL 2008 mode configured for project sources" "OK"
-
-#----------------------------------------------------------------
-# Add constraints files
-#----------------------------------------------------------------
-
-
 # Set packages libraries if any
 #set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
 #update_compile_order -fileset sources_1
@@ -115,41 +124,43 @@ print_status "Add IPI design" "OK"
 set_property top $prj_name [current_fileset]
 update_compile_order -fileset sources_1
 
-# Add testbench sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
-	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
-	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+# Add simulation sources
+set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
+set verilog_sim_file_list [findFiles $sim_src_dir *.v]
+set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
+
+if {$hdl_sim_file_list != ""} {
+  add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+  update_compile_order -fileset sim_1
+  print_status "Add simulation sources" "OK"
+} else {
+  print_status "No simulation sources to be added" "WARNING"
 }
-set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
-add_files -fileset sim_1 -norecurse $hdl_sim_file_list
-update_compile_order -fileset sim_1
-print_status "Add testbench sources" "OK"
 
 foreach j $vhdl_sim_file_list {
-    set_property file_type {VHDL 2008} [get_files  $j]
-    print_status "VHDL 2008 mode configured for the file $j" "OK"
+  set_property file_type {VHDL 2008} [get_files $j]
+  print_status "VHDL 2008 mode configured for the file $j" "OK"
 }
-print_status "VHDL 2008 mode configured for testbench sources" "OK"
+print_status "VHDL 2008 mode configured for simulation sources" "OK"
 
 # Add packages sources
 	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
 	add_files -norecurse $vhdl_pkg_file_list
 	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
+		set_property library xil_defaultlib [get_files $j]
 	}
 print_status "Add packages sources" "OK"
 print_status "VHDL 2008 mode configured for packages sources" "OK"
 
 # Add SoC wrapper sources files
-	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps_safe/src/hdl *.vhd]
 	add_files -norecurse $vhdl_soc_file_list
 	foreach j $vhdl_soc_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
+		set_property file_type {VHDL 2008} [get_files $j]
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/open_prj_scalp_safe_firmware.sh

@@ -15,9 +15,9 @@
 # Project Name: scalp_safe_firmware
 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
 # Tool version: 2020.2
-# Description: Create Vivado project
+# Description: Open Vivado project GUI
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 

designs/vivado/scalp_safe_firmware/2020.2/lin64/.scripts/utils.tcl

@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: Project management utilities
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:12
 #
 ##################################################################################
 

designs/vivado/scalp_safe_firmware/2020.2/lin64/setup.sh

@@ -15,7 +15,7 @@
 # Tool version: 2020.2
 # Description: TCL script creating aliases for Vivado project management scripts
 #
-# Last update: 2021-01-18 08:46:36
+# Last update: 2021-10-14 11:46:11
 #
 ##################################################################################
 
@@ -25,6 +25,4 @@ alias clean_project='cd .scripts && ./clean_prj_scalp_safe_firmware.sh && cd ..'
 alias export_hw='cd .scripts && ./export_hw_scalp_safe_firmware.sh && cd ..'
 alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_safe_firmware.sh && cd ..'
 alias load_bitstream='cd .scripts && ./load_bitstream_scalp_safe_firmware.sh && cd ..'
-alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_safe_firmware.sh && cd ..'
-alias load_sw_app='cd .scripts && ./load_sw_app_scalp_safe_firmware.sh && cd ..'
 alias open_gui='cd .scripts && ./open_prj_scalp_safe_firmware.sh && cd ..'

designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: scalp_firmware
 --
--- Last update: 2021-10-08
+-- Last update: 2021-10-14
 --
 ---------------------------------------------------------------------------------
 
@@ -336,28 +336,9 @@ begin
                 Spi1SclkxCO         => Pll2V5ClkuWirexCO,
                 -- MIO
                 FIXED_IO_mio        => MIOxDIO,
-                UserClkxCI          => PSSysClkxC,
-                UserResetxRANI      => PSSysResetxR,
-                -- Scalp Axi Lite interface and IRQ
-                LocalNetAddrxDO     => open,
+                -- Scalp
                 RGBLed0xDO          => RgbLedsCtrlPortxD,
-                RGBLed1xDO          => open,
-                DMARXm2sxDI         => C_NO_AXI4_M2S,
-                DMARXs2mxDO         => open,
-                DMATXm2sxDO         => open,
-                DMATXs2mxDI         => C_NO_AXI4_S2M,
-                WestRXM2SxDI        => C_NO_AXI4_M2S,
-                WestRXS2MxDI        => C_NO_AXI4_S2M,
-                WestTXM2SxDI        => C_NO_AXI4_M2S,
-                WestTXS2MxDI        => C_NO_AXI4_S2M,
-                EastRXM2SxDI        => C_NO_AXI4_M2S,
-                EastRXS2MxDI        => C_NO_AXI4_S2M,
-                EastTXM2SxDI        => C_NO_AXI4_M2S,
-                EastTXS2MxDI        => C_NO_AXI4_S2M,
-                LocalRXM2SxDI       => C_NO_AXI4_M2S,
-                LocalRXS2MxDI       => C_NO_AXI4_S2M,
-                LocalTXM2SxDI       => C_NO_AXI4_M2S,
-                LocalTXS2MxDI       => C_NO_AXI4_S2M);
+                RGBLed1xDO          => open);
 
     end block ProcessingSystemxB;
 

designs/vivado/scalp_safe_firmware/2020.2/src/ipi_tcl/scalp_safe_firmware_ipi.tcl

-source "../../../../../../soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl"
\ No newline at end of file
+source "../../../../../../soc/vivado/scalp_zynqps_safe/2020.2/src/ipi_tcl/scalp_zynqps_safe_ipi.tcl"

tools/config/scalp_safe_firmware.json

@@ -23,10 +23,12 @@
     },   
     "components" : {
         "packages" : {
-            "axi4_pkg"          : "enable"
+            "axi4_pkg" : {
+                "enable" : "true"
+            }
         },
         "soc" : {
-            "scalp_zynqps" : "enable"
+            "scalp_zynqps_safe" : "enable"
         }
     }
 }