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Commit 35d117f7 authored by joachim.schmidt's avatar joachim.schmidt
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Updated scalp_safe_firmware with new SoC block design

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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_safe_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Git ignore file
#
# Last update: 2021-10-14 11:46:11
#
##################################################################################
# Ignore generated project directory
scalp_safe_firmware
.scripts/scalp_zynqps_safe
.scripts/.Xil
\ No newline at end of file
...@@ -15,23 +15,33 @@ ...@@ -15,23 +15,33 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: Console color print utility # Description: Console color print utility
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
# Try to set a variable with an execution command
# If the command fails, set the variable to an empty string
# cmd - The command to be executed
# return The variable to be set
proc try_setexec {cmd} {
set code [catch { set var [exec {*}$cmd] } ]
if { $code != 0 } { set var "" }
return ${var}
}
# Text attributes # Text attributes
set RESET [exec tput sgr0] set RESET [try_setexec "tput sgr0"]
set BOLD [exec tput bold] set BOLD [try_setexec "tput bold"]
set ITALIC [exec tput sitm] set ITALIC [try_setexec "tput sitm"]
set BLINK [exec tput blink] set BLINK [try_setexec "tput blink"]
set HIGHL [exec tput smso] set HIGHL [try_setexec "tput smso"]
# Text colors # Text colors
set RED [exec tput setaf 1] set RED [try_setexec "tput setaf 1"]
set GREEN [exec tput setaf 2] set GREEN [try_setexec "tput setaf 2"]
set YELLOW [exec tput setaf 3] set YELLOW [try_setexec "tput setaf 3"]
set BLUE [exec tput setaf 4] set BLUE [try_setexec "tput setaf 4"]
set MAGENTA [exec tput setaf 5] set MAGENTA [try_setexec "tput setaf 5"]
set CYAN [exec tput setaf 6] set CYAN [try_setexec "tput setaf 6"]
set WHITE [exec tput setaf 7] set WHITE [try_setexec "tput setaf 7"]
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: Cleanup project directory # Description: Cleanup project directory
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
...@@ -31,10 +31,5 @@ rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null ...@@ -31,10 +31,5 @@ rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory # Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_safe_firmware/ 2> /dev/null rm -rf ${PRJ_DIR}/scalp_safe_firmware/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done" echo "> Done"
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: Create Vivado project # Description: Create Vivado project
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_safe_firmware' # Description: TCL script for re-creating Vivado project 'scalp_safe_firmware'
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
...@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}] ...@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project # Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src" set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw" set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
set comp_dir "${ip_dir}/$prj_name" set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src" set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw" set pkg_src_dir "${PKG_DIR}/hw"
...@@ -49,19 +50,44 @@ set_property target_language VHDL [current_project] ...@@ -49,19 +50,44 @@ set_property target_language VHDL [current_project]
print_status "Create project" "OK" print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included # Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset] set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
update_ip_catalog update_ip_catalog
#---------------------------------------------------------------- #----------------------------------------------------------------
# Add project sources # Add project sources
#---------------------------------------------------------------- #----------------------------------------------------------------
# Get HDL source files directory
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources set hdl_src_dir "${src_dir}/hdl"
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd] set sim_src_dir "${src_dir}/sim"
set verilog_src_file_list [findFiles $src_dir/hdl *.v] } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list] # components sources are stored in an external directory
set hdl_src_dir "${comp_src_dir}/hdl"
set sim_src_dir "${comp_src_dir}/sim"
}
# add HDL source files
set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
set verilog_src_file_list [findFiles $hdl_src_dir *.v]
set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
if {$hdl_src_file_list != ""} {
add_files -norecurse $hdl_src_file_list add_files -norecurse $hdl_src_file_list
} else {
print_status "No sources to be added" "WARNING"
}
# Set VHDL version
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Add constraint files and IPs source files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC) # add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_safe_firmware.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_safe_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_safe_firmware.xdc] set_property is_enabled true [get_files $src_dir/constrs/scalp_safe_firmware.xdc]
...@@ -72,33 +98,16 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc ...@@ -72,33 +98,16 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/ibert_constraints.xdc
add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc] set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
# add IPs source file # add IPs source files
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { } elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory # add IPs source files
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
# add IP-XACT source file # add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml #add_files -norecurse $comp_dir/component.xml
} }
print_status "Add project sources" "OK" print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
#----------------------------------------------------------------
# Add constraints files
#----------------------------------------------------------------
# Set packages libraries if any # Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd] #set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1 #update_compile_order -fileset sources_1
...@@ -115,24 +124,25 @@ print_status "Add IPI design" "OK" ...@@ -115,24 +124,25 @@ print_status "Add IPI design" "OK"
set_property top $prj_name [current_fileset] set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1
# Add testbench sources # Add simulation sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} { set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd] set verilog_sim_file_list [findFiles $sim_src_dir *.v]
set verilog_sim_file_list [findFiles $src_dir/sim *.v] set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} { set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v] if {$hdl_sim_file_list != ""} {
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
add_files -fileset sim_1 -norecurse $hdl_sim_file_list add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1 update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK" print_status "Add simulation sources" "OK"
} else {
print_status "No simulation sources to be added" "WARNING"
}
foreach j $vhdl_sim_file_list { foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
} }
print_status "VHDL 2008 mode configured for testbench sources" "OK" print_status "VHDL 2008 mode configured for simulation sources" "OK"
# Add packages sources # Add packages sources
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd] set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
...@@ -141,12 +151,13 @@ print_status "VHDL 2008 mode configured for testbench sources" "OK" ...@@ -141,12 +151,13 @@ print_status "VHDL 2008 mode configured for testbench sources" "OK"
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK" print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j] set_property is_enabled true [get_files $j]
set_property library xil_defaultlib [get_files $j]
} }
print_status "Add packages sources" "OK" print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK" print_status "VHDL 2008 mode configured for packages sources" "OK"
# Add SoC wrapper sources files # Add SoC wrapper sources files
set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd] set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps_safe/src/hdl *.vhd]
add_files -norecurse $vhdl_soc_file_list add_files -norecurse $vhdl_soc_file_list
foreach j $vhdl_soc_file_list { foreach j $vhdl_soc_file_list {
set_property file_type {VHDL 2008} [get_files $j] set_property file_type {VHDL 2008} [get_files $j]
......
...@@ -15,9 +15,9 @@ ...@@ -15,9 +15,9 @@
# Project Name: scalp_safe_firmware # Project Name: scalp_safe_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2 # Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2 # Tool version: 2020.2
# Description: Create Vivado project # Description: Open Vivado project GUI
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: Project management utilities # Description: Project management utilities
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:12
# #
################################################################################## ##################################################################################
......
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
# Tool version: 2020.2 # Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts # Description: TCL script creating aliases for Vivado project management scripts
# #
# Last update: 2021-01-18 08:46:36 # Last update: 2021-10-14 11:46:11
# #
################################################################################## ##################################################################################
...@@ -25,6 +25,4 @@ alias clean_project='cd .scripts && ./clean_prj_scalp_safe_firmware.sh && cd ..' ...@@ -25,6 +25,4 @@ alias clean_project='cd .scripts && ./clean_prj_scalp_safe_firmware.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_scalp_safe_firmware.sh && cd ..' alias export_hw='cd .scripts && ./export_hw_scalp_safe_firmware.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_safe_firmware.sh && cd ..' alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_safe_firmware.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_scalp_safe_firmware.sh && cd ..' alias load_bitstream='cd .scripts && ./load_bitstream_scalp_safe_firmware.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_safe_firmware.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_scalp_safe_firmware.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_scalp_safe_firmware.sh && cd ..' alias open_gui='cd .scripts && ./open_prj_scalp_safe_firmware.sh && cd ..'
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2020.2 -- Tool version: 2020.2
-- Description: scalp_firmware -- Description: scalp_firmware
-- --
-- Last update: 2021-10-08 -- Last update: 2021-10-14
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -336,28 +336,9 @@ begin ...@@ -336,28 +336,9 @@ begin
Spi1SclkxCO => Pll2V5ClkuWirexCO, Spi1SclkxCO => Pll2V5ClkuWirexCO,
-- MIO -- MIO
FIXED_IO_mio => MIOxDIO, FIXED_IO_mio => MIOxDIO,
UserClkxCI => PSSysClkxC, -- Scalp
UserResetxRANI => PSSysResetxR,
-- Scalp Axi Lite interface and IRQ
LocalNetAddrxDO => open,
RGBLed0xDO => RgbLedsCtrlPortxD, RGBLed0xDO => RgbLedsCtrlPortxD,
RGBLed1xDO => open, RGBLed1xDO => open);
DMARXm2sxDI => C_NO_AXI4_M2S,
DMARXs2mxDO => open,
DMATXm2sxDO => open,
DMATXs2mxDI => C_NO_AXI4_S2M,
WestRXM2SxDI => C_NO_AXI4_M2S,
WestRXS2MxDI => C_NO_AXI4_S2M,
WestTXM2SxDI => C_NO_AXI4_M2S,
WestTXS2MxDI => C_NO_AXI4_S2M,
EastRXM2SxDI => C_NO_AXI4_M2S,
EastRXS2MxDI => C_NO_AXI4_S2M,
EastTXM2SxDI => C_NO_AXI4_M2S,
EastTXS2MxDI => C_NO_AXI4_S2M,
LocalRXM2SxDI => C_NO_AXI4_M2S,
LocalRXS2MxDI => C_NO_AXI4_S2M,
LocalTXM2SxDI => C_NO_AXI4_M2S,
LocalTXS2MxDI => C_NO_AXI4_S2M);
end block ProcessingSystemxB; end block ProcessingSystemxB;
......
source "../../../../../../soc/vivado/scalp_zynqps/2020.2/src/ipi_tcl/scalp_zynqps_ipi.tcl" source "../../../../../../soc/vivado/scalp_zynqps_safe/2020.2/src/ipi_tcl/scalp_zynqps_safe_ipi.tcl"
\ No newline at end of file
################################################################ ################################################################
# This is a generated script based on design: scalp_zynqps # This is a generated script based on design: scalp_zynqps_safe
# #
# Though there are limitations about the generated script, # Though there are limitations about the generated script,
# the main purpose of this utility is to make learning # the main purpose of this utility is to make learning
...@@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { ...@@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
################################################################ ################################################################
# To test this script, run the following commands from Vivado Tcl console: # To test this script, run the following commands from Vivado Tcl console:
# source scalp_zynqps_script.tcl # source scalp_zynqps_safe_script.tcl
# If there is no project opened, this script will create a # If there is no project opened, this script will create a
# project, but make sure you do not have an existing project # project, but make sure you do not have an existing project
...@@ -122,17 +122,11 @@ set bCheckIPsPassed 1 ...@@ -122,17 +122,11 @@ set bCheckIPsPassed 1
set bCheckIPs 1 set bCheckIPs 1
if { $bCheckIPs == 1 } { if { $bCheckIPs == 1 } {
set list_check_ips "\ set list_check_ips "\
xilinx.com:ip:axi_clock_converter:2.1\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:xlconstant:1.1\ xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:processing_system7:5.5\ xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\ xilinx.com:ip:proc_sys_reset:5.0\
hepia.hesge.ch:user:scalp_dma_fifo:1.0\
hepia.hesge.ch:user:scalp_fast_router_registers:1.0\ hepia.hesge.ch:user:scalp_fast_router_registers:1.0\
xilinx.com:ip:system_ila:1.1\
xilinx.com:ip:util_vector_logic:2.0\ xilinx.com:ip:util_vector_logic:2.0\
xilinx.com:ip:vio:3.0\
xilinx.com:ip:xlconcat:2.1\
" "
set list_ips_missing "" set list_ips_missing ""
...@@ -198,57 +192,8 @@ proc create_root_design { parentCell } { ...@@ -198,57 +192,8 @@ proc create_root_design { parentCell } {
# Create interface ports # Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set DMARXxDI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMARXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_TREADY {1} \
CONFIG.HAS_TSTRB {0} \
CONFIG.LAYERED_METADATA {undef} \
CONFIG.TDATA_NUM_BYTES {4} \
CONFIG.TDEST_WIDTH {0} \
CONFIG.TID_WIDTH {0} \
CONFIG.TUSER_WIDTH {0} \
] $DMARXxDI
set DMATXxDO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMATXxDO ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $DMATXxDO
set EastRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastRXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $EastRXxDI
set EastTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 EastTXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $EastTXxDI
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
set LocalRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalRXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $LocalRXxDI
set LocalTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 LocalTXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $LocalTXxDI
set WestRXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestRXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $WestRXxDI
set WestTXxDI [ create_bd_intf_port -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 WestTXxDI ]
set_property -dict [ list \
CONFIG.FREQ_HZ {125000000} \
] $WestTXxDI
# Create ports # Create ports
set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ] set FclkClk0xCO [ create_bd_port -dir O -type clk FclkClk0xCO ]
...@@ -256,44 +201,12 @@ proc create_root_design { parentCell } { ...@@ -256,44 +201,12 @@ proc create_root_design { parentCell } {
CONFIG.FREQ_HZ {125000000} \ CONFIG.FREQ_HZ {125000000} \
] $FclkClk0xCO ] $FclkClk0xCO
set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ] set FclkReset0xRO [ create_bd_port -dir O -from 0 -to 0 FclkReset0xRO ]
set LocalNetAddrxDO [ create_bd_port -dir O -from 31 -to 0 -type data LocalNetAddrxDO ]
set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ] set RGBLed0xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed0xDO ]
set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ] set RGBLed1xDO [ create_bd_port -dir O -from 31 -to 0 -type data RGBLed1xDO ]
set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ] set Spi1MOSIxSO [ create_bd_port -dir O Spi1MOSIxSO ]
set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ] set Spi1SSxSO [ create_bd_port -dir O Spi1SSxSO ]
set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ] set Spi1SclkxCO [ create_bd_port -dir O Spi1SclkxCO ]
set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ] set Usb0VBusPwrFaultxSI [ create_bd_port -dir I Usb0VBusPwrFaultxSI ]
set UserClkxCI [ create_bd_port -dir I -type clk -freq_hz 125000000 UserClkxCI ]
set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {DMATXxDO:DMARXxDI:EastTXxDI:WestRXxDI:WestTXxDI:EastRXxDI:LocalTXxDI:LocalRXxDI} \
] $UserClkxCI
set UserResetxRANI [ create_bd_port -dir I -type rst UserResetxRANI ]
# Create instance: axi_clock_converter_0, and set properties
set axi_clock_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_0 ]
# Create instance: axi_clock_converter_1, and set properties
set axi_clock_converter_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_1 ]
# Create instance: axi_clock_converter_2, and set properties
set axi_clock_converter_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_2 ]
# Create instance: axi_clock_converter_3, and set properties
set axi_clock_converter_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_clock_converter:2.1 axi_clock_converter_3 ]
# Create instance: axi_dma_0, and set properties
set axi_dma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_0 ]
set_property -dict [ list \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
] $axi_dma_0
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {2} \
] $axi_interconnect_0
# Create instance: gnd_constant_0, and set properties # Create instance: gnd_constant_0, and set properties
set gnd_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_0 ] set gnd_constant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_0 ]
...@@ -305,7 +218,7 @@ proc create_root_design { parentCell } { ...@@ -305,7 +218,7 @@ proc create_root_design { parentCell } {
set gnd_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_1 ] set gnd_constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 gnd_constant_1 ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.CONST_VAL {0} \ CONFIG.CONST_VAL {0} \
CONFIG.CONST_WIDTH {30} \ CONFIG.CONST_WIDTH {32} \
] $gnd_constant_1 ] $gnd_constant_1
# Create instance: processing_system7_0, and set properties # Create instance: processing_system7_0, and set properties
...@@ -414,7 +327,7 @@ proc create_root_design { parentCell } { ...@@ -414,7 +327,7 @@ proc create_root_design { parentCell } {
CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \ CONFIG.PCW_IOPLL_CTRL_FBDIV {35} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1750.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \ CONFIG.PCW_IRQ_F2P_INTR {0} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \ CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_PULLUP {enabled} \ CONFIG.PCW_MIO_0_PULLUP {enabled} \
...@@ -749,71 +662,21 @@ proc create_root_design { parentCell } { ...@@ -749,71 +662,21 @@ proc create_root_design { parentCell } {
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
CONFIG.PCW_USE_S_AXI_GP0 {0} \ CONFIG.PCW_USE_S_AXI_GP0 {0} \
CONFIG.PCW_USE_S_AXI_HP0 {1} \ CONFIG.PCW_USE_S_AXI_HP0 {0} \
] $processing_system7_0 ] $processing_system7_0
# Create instance: ps7_0_axi_periph, and set properties # Create instance: ps7_0_axi_periph, and set properties
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.NUM_MI {2} \ CONFIG.NUM_MI {1} \
] $ps7_0_axi_periph ] $ps7_0_axi_periph
# Create instance: rst_ps7_0_125M, and set properties # Create instance: rst_ps7_0_125M, and set properties
set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ] set rst_ps7_0_125M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_125M ]
# Create instance: scalp_dma_fifo_rx_0, and set properties
set scalp_dma_fifo_rx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_rx_0 ]
# Create instance: scalp_dma_fifo_tx_0, and set properties
set scalp_dma_fifo_tx_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_dma_fifo:1.0 scalp_dma_fifo_tx_0 ]
# Create instance: scalp_fast_router_registers_0, and set properties # Create instance: scalp_fast_router_registers_0, and set properties
set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.0 scalp_fast_router_registers_0 ] set scalp_fast_router_registers_0 [ create_bd_cell -type ip -vlnv hepia.hesge.ch:user:scalp_fast_router_registers:1.0 scalp_fast_router_registers_0 ]
# Create instance: system_ila_0, and set properties
set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
set_property -dict [ list \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_BRAM_CNT {3} \
CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_MON_TYPE {MIX} \
CONFIG.C_NUM_MONITOR_SLOTS {8} \
CONFIG.C_NUM_OF_PROBES {9} \
CONFIG.C_PROBE0_MU_CNT {2} \
CONFIG.C_PROBE1_MU_CNT {2} \
CONFIG.C_PROBE2_MU_CNT {2} \
CONFIG.C_PROBE3_MU_CNT {2} \
CONFIG.C_PROBE4_MU_CNT {2} \
CONFIG.C_PROBE5_MU_CNT {2} \
CONFIG.C_PROBE6_MU_CNT {2} \
CONFIG.C_PROBE7_MU_CNT {2} \
CONFIG.C_PROBE8_MU_CNT {2} \
CONFIG.C_SLOT {7} \
CONFIG.C_SLOT_0_APC_EN {0} \
CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \
CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \
CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_1_APC_EN {0} \
CONFIG.C_SLOT_1_AXI_DATA_SEL {1} \
CONFIG.C_SLOT_1_AXI_TRIG_SEL {1} \
CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_4_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_5_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_6_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
CONFIG.C_SLOT_7_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
] $system_ila_0
# Create instance: util_vector_logic_0, and set properties
set util_vector_logic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_0 ]
set_property -dict [ list \
CONFIG.C_OPERATION {or} \
CONFIG.C_SIZE {1} \
CONFIG.LOGO_FILE {data/sym_orgate.png} \
] $util_vector_logic_0
# Create instance: util_vector_logic_1, and set properties # Create instance: util_vector_logic_1, and set properties
set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ] set util_vector_logic_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 util_vector_logic_1 ]
set_property -dict [ list \ set_property -dict [ list \
...@@ -822,107 +685,27 @@ proc create_root_design { parentCell } { ...@@ -822,107 +685,27 @@ proc create_root_design { parentCell } {
CONFIG.LOGO_FILE {data/sym_notgate.png} \ CONFIG.LOGO_FILE {data/sym_notgate.png} \
] $util_vector_logic_1 ] $util_vector_logic_1
# Create instance: vio_0, and set properties
set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ]
set_property -dict [ list \
CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
CONFIG.C_NUM_PROBE_IN {0} \
] $vio_0
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ]
set_property -dict [ list \
CONFIG.IN2_WIDTH {1} \
CONFIG.IN3_WIDTH {1} \
CONFIG.NUM_PORTS {2} \
] $xlconcat_0
# Create instance: xlconcat_1, and set properties
set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ]
set_property -dict [ list \
CONFIG.IN2_WIDTH {30} \
CONFIG.NUM_PORTS {3} \
] $xlconcat_1
# Create instance: xlconcat_2, and set properties
set xlconcat_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_2 ]
set_property -dict [ list \
CONFIG.IN2_WIDTH {30} \
CONFIG.NUM_PORTS {3} \
] $xlconcat_2
# Create interface connections # Create interface connections
connect_bd_intf_net -intf_net Conn [get_bd_intf_ports EastRXxDI] [get_bd_intf_pins system_ila_0/SLOT_2_AXIS]
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_ports EastTXxDI] [get_bd_intf_pins system_ila_0/SLOT_3_AXIS]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_ports WestRXxDI] [get_bd_intf_pins system_ila_0/SLOT_4_AXIS]
connect_bd_intf_net -intf_net Conn3 [get_bd_intf_ports WestTXxDI] [get_bd_intf_pins system_ila_0/SLOT_5_AXIS]
connect_bd_intf_net -intf_net Conn4 [get_bd_intf_ports LocalRXxDI] [get_bd_intf_pins system_ila_0/SLOT_6_AXIS]
connect_bd_intf_net -intf_net Conn5 [get_bd_intf_ports LocalTXxDI] [get_bd_intf_pins system_ila_0/SLOT_7_AXIS]
connect_bd_intf_net -intf_net DMARXxDI_1 [get_bd_intf_ports DMARXxDI] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMARXxDI]
connect_bd_intf_net -intf_net axi_clock_converter_0_M_AXI [get_bd_intf_pins axi_clock_converter_0/M_AXI] [get_bd_intf_pins axi_dma_0/S_AXI_LITE]
connect_bd_intf_net -intf_net axi_clock_converter_1_M_AXI [get_bd_intf_pins axi_clock_converter_1/M_AXI] [get_bd_intf_pins axi_interconnect_0/S00_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_2_M_AXI [get_bd_intf_pins axi_clock_converter_2/M_AXI] [get_bd_intf_pins axi_interconnect_0/S01_AXI]
connect_bd_intf_net -intf_net axi_clock_converter_3_M_AXI [get_bd_intf_pins axi_clock_converter_3/M_AXI] [get_bd_intf_pins scalp_fast_router_registers_0/SAxiLitexDIO]
connect_bd_intf_net -intf_net axi_dma_0_M_AXIS_MM2S [get_bd_intf_pins axi_dma_0/M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI]
connect_bd_intf_net -intf_net [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMARXxDI] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_dma_0_M_AXIS_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_MM2S [get_bd_intf_pins axi_clock_converter_1/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_MM2S]
connect_bd_intf_net -intf_net axi_dma_0_M_AXI_S2MM [get_bd_intf_pins axi_clock_converter_2/S_AXI] [get_bd_intf_pins axi_dma_0/M_AXI_S2MM]
connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0]
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_clock_converter_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins scalp_fast_router_registers_0/SAxiLitexDIO]
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins axi_clock_converter_3/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net scalp_dma_fifo_rx_0_DMATXxDO [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO]
connect_bd_intf_net -intf_net [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_rx_0/DMATXxDO] [get_bd_intf_pins system_ila_0/SLOT_1_AXIS]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets scalp_dma_fifo_rx_0_DMATXxDO]
connect_bd_intf_net -intf_net scalp_dma_fifo_tx_0_DMATXxDO [get_bd_intf_ports DMATXxDO] [get_bd_intf_pins scalp_dma_fifo_tx_0/DMATXxDO]
# Create port connections # Create port connections
connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT] connect_bd_net -net USB0_VBUS_PWRFAULT_0_1 [get_bd_ports Usb0VBusPwrFaultxSI] [get_bd_pins processing_system7_0/USB0_VBUS_PWRFAULT]
connect_bd_net -net UserClkxCI_1 [get_bd_ports UserClkxCI] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_clock_converter_1/s_axi_aclk] [get_bd_pins axi_clock_converter_2/s_axi_aclk] [get_bd_pins axi_clock_converter_3/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins scalp_dma_fifo_rx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_rx_0/TXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/RXClkxCI] [get_bd_pins scalp_dma_fifo_tx_0/TXClkxCI] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI] [get_bd_pins system_ila_0/clk]
connect_bd_net -net UserResetxRANI_1 [get_bd_ports UserResetxRANI] [get_bd_pins axi_clock_converter_0/m_axi_aresetn] [get_bd_pins axi_clock_converter_1/s_axi_aresetn] [get_bd_pins axi_clock_converter_2/s_axi_aresetn] [get_bd_pins axi_clock_converter_3/m_axi_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins scalp_dma_fifo_rx_0/RXRstxRANI] [get_bd_pins scalp_dma_fifo_tx_0/RXRstxRANI] [get_bd_pins scalp_fast_router_registers_0/SAxiRstxRANI] [get_bd_pins system_ila_0/resetn]
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins xlconcat_0/In0]
connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1]
connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant_0/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I] connect_bd_net -net gnd_constant_dout [get_bd_pins gnd_constant_0/dout] [get_bd_pins processing_system7_0/SPI1_MISO_I] [get_bd_pins processing_system7_0/SPI1_MOSI_I] [get_bd_pins processing_system7_0/SPI1_SCLK_I] [get_bd_pins processing_system7_0/SPI1_SS_I]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_clock_converter_1/m_axi_aclk] [get_bd_pins axi_clock_converter_2/m_axi_aclk] [get_bd_pins axi_clock_converter_3/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins vio_0/clk] connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FclkClk0xCO] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_125M/slowest_sync_clk] [get_bd_pins scalp_fast_router_registers_0/SAxiClkxCI]
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_125M/ext_reset_in] [get_bd_pins util_vector_logic_1/Op1]
connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O] connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports Spi1MOSIxSO] [get_bd_pins processing_system7_0/SPI1_MOSI_O]
connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O] connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports Spi1SclkxCO] [get_bd_pins processing_system7_0/SPI1_SCLK_O]
connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O] connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports Spi1SSxSO] [get_bd_pins processing_system7_0/SPI1_SS_O]
connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins axi_clock_converter_0/s_axi_aresetn] [get_bd_pins axi_clock_converter_1/m_axi_aresetn] [get_bd_pins axi_clock_converter_2/m_axi_aresetn] [get_bd_pins axi_clock_converter_3/s_axi_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_interconnect_0/S01_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] connect_bd_net -net rst_ps7_0_125M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_125M/peripheral_aresetn] [get_bd_pins scalp_fast_router_registers_0/SAxiRstxRANI]
connect_bd_net -net scalp_dma_fifo_rx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe2] [get_bd_pins xlconcat_2/In0]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgEmptyxSO]
connect_bd_net -net scalp_dma_fifo_rx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_rx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe3] [get_bd_pins xlconcat_2/In1]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_ProgFullxSO]
connect_bd_net -net scalp_dma_fifo_rx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXRrDataCntxDI] [get_bd_pins system_ila_0/probe1]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_RdDataCntxDO]
connect_bd_net -net scalp_dma_fifo_rx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_rx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXWrDataCntxDI] [get_bd_pins system_ila_0/probe0]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_rx_0_WrDataCntxDO]
connect_bd_net -net scalp_dma_fifo_tx_0_ProgEmptyxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgEmptyxSO] [get_bd_pins system_ila_0/probe6] [get_bd_pins xlconcat_1/In0]
connect_bd_net -net scalp_dma_fifo_tx_0_ProgFullxSO [get_bd_pins scalp_dma_fifo_tx_0/ProgFullxSO] [get_bd_pins system_ila_0/probe7] [get_bd_pins xlconcat_1/In1]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_ProgFullxSO]
connect_bd_net -net scalp_dma_fifo_tx_0_RdDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/RdDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXRrDataCntxDI] [get_bd_pins system_ila_0/probe5]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_RdDataCntxDO]
connect_bd_net -net scalp_dma_fifo_tx_0_WrDataCntxDO [get_bd_pins scalp_dma_fifo_tx_0/WrDataCntxDO] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXWrDataCntxDI] [get_bd_pins system_ila_0/probe4]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets scalp_dma_fifo_tx_0_WrDataCntxDO]
connect_bd_net -net scalp_fast_router_re_0_RGBLed0xDO [get_bd_ports RGBLed0xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed0xDO] connect_bd_net -net scalp_fast_router_re_0_RGBLed0xDO [get_bd_ports RGBLed0xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed0xDO]
connect_bd_net -net scalp_fast_router_re_0_RGBLed1xDO [get_bd_ports RGBLed1xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed1xDO] connect_bd_net -net scalp_fast_router_re_0_RGBLed1xDO [get_bd_ports RGBLed1xDO] [get_bd_pins scalp_fast_router_registers_0/RGBLed1xDO]
connect_bd_net -net scalp_fast_router_registers_0_LocalNetAddrxDO [get_bd_ports LocalNetAddrxDO] [get_bd_pins scalp_fast_router_registers_0/LocalNetAddrxDO] connect_bd_net -net util_vector_logic_1_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net util_vector_logic_0_Res [get_bd_ports FclkReset0xRO] [get_bd_pins util_vector_logic_0/Res] connect_bd_net -net xlconcat_1_dout [get_bd_pins gnd_constant_1/dout] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXRrDataCntxDI] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXStatusxDI] [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXWrDataCntxDI] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXRrDataCntxDI] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXStatusxDI] [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXWrDataCntxDI]
connect_bd_net -net util_vector_logic_1_Res [get_bd_pins util_vector_logic_0/Op1] [get_bd_pins util_vector_logic_1/Res]
connect_bd_net -net vio_0_probe_out0 [get_bd_pins util_vector_logic_0/Op2] [get_bd_pins vio_0/probe_out0]
connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins system_ila_0/probe8] [get_bd_pins xlconcat_0/dout]
set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_nets xlconcat_0_dout]
connect_bd_net -net xlconcat_1_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoTXStatusxDI] [get_bd_pins xlconcat_1/dout]
connect_bd_net -net xlconcat_2_dout [get_bd_pins scalp_fast_router_registers_0/DMAFifoRXStatusxDI] [get_bd_pins xlconcat_2/dout]
connect_bd_net -net xlconstant_0_dout [get_bd_pins gnd_constant_1/dout] [get_bd_pins xlconcat_1/In2] [get_bd_pins xlconcat_2/In2]
# Create address segments # Create address segments
assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x0C000000 -range 0x04000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] -force
assign_bd_address -offset 0x40400000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_dma_0/S_AXI_LITE/Reg] -force
assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_fast_router_registers_0/SAxiLitexDIO/reg0] -force assign_bd_address -offset 0x43C00000 -range 0x00001000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs scalp_fast_router_registers_0/SAxiLitexDIO/reg0] -force
......
...@@ -23,10 +23,12 @@ ...@@ -23,10 +23,12 @@
}, },
"components" : { "components" : {
"packages" : { "packages" : {
"axi4_pkg" : "enable" "axi4_pkg" : {
"enable" : "true"
}
}, },
"soc" : { "soc" : {
"scalp_zynqps" : "enable" "scalp_zynqps_safe" : "enable"
} }
} }
} }
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