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Commit 43f6ce9f authored by joachim.schmidt's avatar joachim.schmidt
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Updated the scalp_firmware project with packet control through an AXI Lite interface.

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......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Git ignore file
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Console color print utility
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Cleanup project directory
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Create Vivado project
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......@@ -113,6 +113,13 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_rx_link_layer/src/hdl *.vhd]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_axis_fifo_wrapper/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
......@@ -139,6 +146,7 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.v
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
read_ip ${ip_dir}/scalp_axis_fifo_wrapper/src/ip_core/scalp_axis_fifo/scalp_axis_fifo.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/north_channel/north_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/south_channel/south_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Export the hardware design to SDK
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Export the hardware design to Vitis SDK
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Generate bitstream file
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: TCL script used to generate bitstream file
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Load bitstream file
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script used to load FPGA bitstream
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Open Vivado project GUI
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Project management utilities
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 11:15:20
#
##################################################################################
......
......@@ -252,3 +252,5 @@ set_operating_conditions -airflow 0 -heatsink none -board small
......@@ -32,3 +32,5 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: Testbench for scalp_firmware
--
-- Last update: 2021-05-17 08:38:48
-- Last update: 2021-05-21 08:30:39
--
---------------------------------------------------------------------------------
......
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Console color print utility
#
# Last update: 2021-05-17 08:38:48
# Last update: 2021-05-21 08:30:39
#
##################################################################################
......
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