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Commit 5854f55e authored by joachim.schmidt's avatar joachim.schmidt
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Updated scalp_fifo_double_register.vhd

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ips/hw/scalp_router/src/hdl/scalp_fifo_double_register.vhd
+ 37
− 104
View file @ 5854f55e
...@@ -26,11 +26,10 @@ use ieee.numeric_std.all; ...@@ -26,11 +26,10 @@ use ieee.numeric_std.all;
--use ieee.std_logic_arith.all; --use ieee.std_logic_arith.all;
--use ieee.std_logic_misc.all; --use ieee.std_logic_misc.all;
--library UNISIM; library UNISIM;
--use UNISIM.VCOMPONENTS.all; use UNISIM.VCOMPONENTS.all;
use work.axi4_pkg.all; use work.axi4_pkg.all;
use work.scalp_misc.all;
entity scalp_fifo_double_register is entity scalp_fifo_double_register is
...@@ -60,7 +59,6 @@ architecture behavioral of scalp_fifo_double_register is ...@@ -60,7 +59,6 @@ architecture behavioral of scalp_fifo_double_register is
-- Axis Ready -- Axis Ready
signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M; signal Axiss2m1xDN : t_axi4s2m := C_NO_AXI4_S2M;
signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M; signal Axiss2m1xDP : t_axi4s2m := C_NO_AXI4_S2M;
signal MUX3SelectxD : std_ulogic := '0';
-- Attributes -- Attributes
attribute mark_debug : string; attribute mark_debug : string;
...@@ -82,8 +80,6 @@ architecture behavioral of scalp_fifo_double_register is ...@@ -82,8 +80,6 @@ architecture behavioral of scalp_fifo_double_register is
attribute keep of Axiss2m1xDN : signal is "true"; attribute keep of Axiss2m1xDN : signal is "true";
attribute mark_debug of Axiss2m1xDP : signal is "true"; attribute mark_debug of Axiss2m1xDP : signal is "true";
attribute keep of Axiss2m1xDP : signal is "true"; attribute keep of Axiss2m1xDP : signal is "true";
attribute mark_debug of MUX3SelectxD : signal is "true";
attribute keep of MUX3SelectxD : signal is "true";
begin -- architecture behavioral begin -- architecture behavioral
...@@ -96,10 +92,18 @@ begin -- architecture behavioral ...@@ -96,10 +92,18 @@ begin -- architecture behavioral
-- S2M -- S2M
Axiss2mLinkInxAS : Axiss2m1xDN <= Axiss2mLinkxDI; Axiss2mLinkInxAS : Axiss2m1xDN <= Axiss2mLinkxDI;
Axiss2mLinkOutxAS : Axiss2mLinkxDO <= Axiss2m1xDP; Axiss2mLinkOutxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
MUX3SelectxAS : MUX3SelectxD <= not Axiss2mLinkxDI.ReadyxS;
end block EntityIOxB; end block EntityIOxB;
MUXxB : block is
begin -- block MUXxB
MUX1xAS : Axism2s1xDN <= Axism2s0xD when Axiss2m1xDP.ReadyxS = '1' else Axism2s1xDP;
MUX2xAS : Axism2s2xDN <= Axism2s0xD when Axiss2m1xDN.ReadyxS = '1' else Axism2s2xDP;
MUX3xAS : Axism2s3xD <= Axism2s1xDP when Axiss2m1xDP.ReadyxS = '1' else Axism2s2xDP;
end block MUXxB;
RegistersxP : process (SysClkxCI, SysRstxRNAI) is RegistersxP : process (SysClkxCI, SysRstxRNAI) is
begin -- process RegistersxP begin -- process RegistersxP
if SysRstxRNAI = '0' then if SysRstxRNAI = '0' then
...@@ -117,75 +121,4 @@ begin -- architecture behavioral ...@@ -117,75 +121,4 @@ begin -- architecture behavioral
end if; end if;
end process RegistersxP; end process RegistersxP;
MUXxB : block is
begin -- block MUXxB
MUX1xAS : Axism2s1xDN <= Axism2s0xD when Axiss2m1xDP.ReadyxS = '1' else Axism2s1xDP;
MUX2xAS : Axism2s2xDN <= Axism2s0xD when Axiss2m1xDN.ReadyxS = '1' else Axism2s2xDP;
MUX3xAS : Axism2s3xD <= Axism2s1xDP when MUX3SelectxD = '1'else Axism2s2xDP;
end block MUXxB;
-- EntityIOxB : block is
-- begin -- block EntityIOxB
-- -- Axis m2s
-- Axism2s0FromxAS : Axism2s0xD <= Axism2sLinkxDI;
-- Axism2s3ToxAS : Axism2sLinkxDO <= Axism2s3xD;
-- -- Axis s2m
-- Axiss2m0FromxAS : Axiss2m0xD <= Axiss2mLinkxDI;
-- Axiss2m1FromxAS : Axiss2m1xDN <= Axiss2m0xD;
-- Axiss2m1ToxAS : Axiss2mLinkxDO <= Axiss2m1xDP;
-- end block EntityIOxB;
-- AsyncStatementsxB : block is
-- begin -- block AsyncStatementsxB
-- Axism2s3FromxAS : Axism2s3xD <= Axism2s1xDP when
-- (Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1') or
-- (Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '1') else
-- Axism2s2xDP;
-- end block AsyncStatementsxB;
-- UpdateRegxP : process (SysClkxCI, SysRstxRNAI) is
-- begin -- process UpdateRegxP
-- if SysRstxRNAI = '0' then
-- -- Axis m2s
-- Axism2s1xDP <= C_NO_AXI4_M2S;
-- Axism2s2xDP <= C_NO_AXI4_M2S;
-- -- Axis s2m
-- Axiss2m1xDP <= C_NO_AXI4_S2M;
-- -- Enable Port
-- -- ScalpFifoEnablexSP <= '0';
-- elsif rising_edge(SysClkxCI) then
-- -- Axis m2s
-- Axism2s1xDP <= Axism2s1xDN;
-- Axism2s2xDP <= Axism2s2xDN;
-- -- Axis s2m
-- Axiss2m1xDP <= Axiss2m1xDN;
-- -- Enable Port
-- -- ScalpFifoEnablexSP <= ScalpFifoEnablexSN;
-- end if;
-- end process UpdateRegxP;
-- TransistionOnReadyxP : process (Axism2s0xD, Axism2s1xDP, Axism2s2xDP,
-- Axiss2m0xD.ReadyxS, Axiss2m1xDP.ReadyxS) is
-- begin -- process TransistionOnReadyxP
-- -- Defaults values
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s2xDP;
-- if Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '0' then
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s2xDP;
-- elsif Axiss2m0xD.ReadyxS = '0' and Axiss2m1xDP.ReadyxS = '1' then
-- Axism2s1xDN <= Axism2s0xD;
-- Axism2s2xDN <= Axism2s2xDP;
-- elsif Axiss2m0xD.ReadyxS = '1' and Axiss2m1xDP.ReadyxS = '0' then
-- Axism2s1xDN <= Axism2s1xDP;
-- Axism2s2xDN <= Axism2s0xD;
-- else
-- Axism2s1xDN <= Axism2s0xD;
-- Axism2s2xDN <= Axism2s0xD;
-- end if;
-- end process TransistionOnReadyxP;
end architecture behavioral; end architecture behavioral;
ips/hw/scalp_router/src/sim/tb_scalp_fifo_double_register.vhd
+ 55
− 42
View file @ 5854f55e
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2019.1 -- Tool version: 2019.1
-- Description: Testbench for scalp_fifo_double_register. -- Description: Testbench for scalp_fifo_double_register.
-- --
-- Last update: 2020-02-21 -- Last update: 2021-05-18
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
library ieee; library ieee;
...@@ -33,9 +33,10 @@ use ieee.math_real.all; ...@@ -33,9 +33,10 @@ use ieee.math_real.all;
--use UNISIM.VCOMPONENTS.all; --use UNISIM.VCOMPONENTS.all;
library work; library work;
use work.aurora_axi4_pkg.all; -- use work.aurora_axi4_pkg.all;
use work.scalp_misc.all; use work.axi4_pkg.all;
use work.scalp_utility.all; -- use work.scalp_misc.all;
-- use work.scalp_utility.all;
entity tb_scalp_fifo_double_register is entity tb_scalp_fifo_double_register is
...@@ -47,13 +48,10 @@ architecture testbench of tb_scalp_fifo_double_register is ...@@ -47,13 +48,10 @@ architecture testbench of tb_scalp_fifo_double_register is
component scalp_fifo_double_register is component scalp_fifo_double_register is
port ( port (
-- System Clock and Reset
SysClkxCI : in std_ulogic; SysClkxCI : in std_ulogic;
SysRstxRNAI : in std_ulogic; SysRstxRNAI : in std_ulogic;
-- Axis Ports (Slave Side)
Axism2sLinkxDI : in t_axi4m2s; Axism2sLinkxDI : in t_axi4m2s;
Axiss2mLinkxDO : out t_axi4s2m; Axiss2mLinkxDO : out t_axi4s2m;
-- Axis Ports (Master Side)
Axism2sLinkxDO : out t_axi4m2s; Axism2sLinkxDO : out t_axi4m2s;
Axiss2mLinkxDI : in t_axi4s2m); Axiss2mLinkxDI : in t_axi4s2m);
end component scalp_fifo_double_register; end component scalp_fifo_double_register;
...@@ -76,7 +74,7 @@ begin -- architecture testbench ...@@ -76,7 +74,7 @@ begin -- architecture testbench
AsyncStatementsxB : block is AsyncStatementsxB : block is
begin -- block AsyncStatementsxB begin -- block AsyncStatementsxB
SysClkxAS : SysClkxC <= not SysClkxC after (C_CLK_PERIOD / 2); SysClkxAS : SysClkxC <= not SysClkxC after (C_CLK_PERIOD / 2);
SysRstxAS : SysRstxRNA <= '1' after (C_CLK_PERIOD * 10); SysRstxAS : SysRstxRNA <= '1' after (C_CLK_PERIOD * 5);
DataxAS : Axism2sLinkInxD.DataxD <= std_ulogic_vector(to_unsigned(CounterxDP, 32)); DataxAS : Axism2sLinkInxD.DataxD <= std_ulogic_vector(to_unsigned(CounterxDP, 32));
end block AsyncStatementsxB; end block AsyncStatementsxB;
...@@ -91,13 +89,10 @@ begin -- architecture testbench ...@@ -91,13 +89,10 @@ begin -- architecture testbench
ScalpFifoDoubleRegisterxI : entity work.scalp_fifo_double_register ScalpFifoDoubleRegisterxI : entity work.scalp_fifo_double_register
port map ( port map (
-- System Clock and Reset
SysClkxCI => SysClkxC, SysClkxCI => SysClkxC,
SysRstxRNAI => SysRstxRNA, SysRstxRNAI => SysRstxRNA,
-- Axis Ports (Slave Side)
Axism2sLinkxDI => Axism2sLinkInxD, Axism2sLinkxDI => Axism2sLinkInxD,
Axiss2mLinkxDO => Axiss2mLinkOutxD, Axiss2mLinkxDO => Axiss2mLinkOutxD,
-- Axis Ports (Master Side)
Axism2sLinkxDO => Axism2sLinkOutxD, Axism2sLinkxDO => Axism2sLinkOutxD,
Axiss2mLinkxDI => Axiss2mLinkInxD); Axiss2mLinkxDI => Axiss2mLinkInxD);
...@@ -128,7 +123,7 @@ begin -- architecture testbench ...@@ -128,7 +123,7 @@ begin -- architecture testbench
wait until (SysRstxRNA = '1'); wait until (SysRstxRNA = '1');
Axism2sLinkInxD.ValidxS <= '1'; Axism2sLinkInxD.ValidxS <= '1';
for i in 0 to 30 loop for i in 0 to 60 loop
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
end loop; -- i end loop; -- i
...@@ -140,17 +135,17 @@ begin -- architecture testbench ...@@ -140,17 +135,17 @@ begin -- architecture testbench
Axism2sLinkInxD.ValidxS <= '1'; Axism2sLinkInxD.ValidxS <= '1';
for i in 0 to 14 loop -- for i in 0 to 14 loop
wait until rising_edge(SysClkxC); -- wait until rising_edge(SysClkxC);
end loop; -- i -- end loop; -- i
Axism2sLinkInxD.ValidxS <= '0'; -- Axism2sLinkInxD.ValidxS <= '0';
for i in 0 to 10 loop -- for i in 0 to 10 loop
wait until rising_edge(SysClkxC); -- wait until rising_edge(SysClkxC);
end loop; -- i -- end loop; -- i
Axism2sLinkInxD.ValidxS <= '1'; -- Axism2sLinkInxD.ValidxS <= '1';
wait; wait;
end process ValidxP; end process ValidxP;
...@@ -160,8 +155,8 @@ begin -- architecture testbench ...@@ -160,8 +155,8 @@ begin -- architecture testbench
Axiss2mLinkInxD.ReadyxS <= '0'; Axiss2mLinkInxD.ReadyxS <= '0';
wait until (SysRstxRNA = '1'); wait until (SysRstxRNA = '1');
Axiss2mLinkInxD.ReadyxS <= '1'; Axiss2mLinkInxD.ReadyxS <= '1';
wait until rising_edge(SysClkxC); -- wait until rising_edge(SysClkxC);
wait until rising_edge(SysClkxC); -- wait until rising_edge(SysClkxC);
for i in 0 to 10 loop for i in 0 to 10 loop
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
...@@ -175,29 +170,47 @@ begin -- architecture testbench ...@@ -175,29 +170,47 @@ begin -- architecture testbench
Axiss2mLinkInxD.ReadyxS <= '1'; Axiss2mLinkInxD.ReadyxS <= '1';
for i in 0 to 40 loop
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
end loop; -- i
Axiss2mLinkInxD.ReadyxS <= '0'; Axiss2mLinkInxD.ReadyxS <= '0';
for i in 0 to 5 loop
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
end loop; -- i
for i in 0 to 20 loop
wait until rising_edge(SysClkxC);
end loop; -- i
Axiss2mLinkInxD.ReadyxS <= '1'; Axiss2mLinkInxD.ReadyxS <= '1';
for i in 0 to 5 loop for i in 0 to 10 loop
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
end loop; -- i end loop; -- i
for i in 0 to 10 loop Axiss2mLinkInxD.ReadyxS <= '0';
wait until rising_edge(SysClkxC); wait until rising_edge(SysClkxC);
end loop; -- i
Axiss2mLinkInxD.ReadyxS <= '1';
-- for i in 0 to 40 loop
-- wait until rising_edge(SysClkxC);
-- end loop; -- i
-- Axiss2mLinkInxD.ReadyxS <= '0';
-- for i in 0 to 5 loop
-- wait until rising_edge(SysClkxC);
-- end loop; -- i
-- for i in 0 to 20 loop
-- wait until rising_edge(SysClkxC);
-- end loop; -- i
-- Axiss2mLinkInxD.ReadyxS <= '1';
-- for i in 0 to 5 loop
-- wait until rising_edge(SysClkxC);
-- end loop; -- i
-- for i in 0 to 10 loop
-- wait until rising_edge(SysClkxC);
-- end loop; -- i
wait; wait;
end process ReadyxP; end process ReadyxP;
......
packages/hw/axi4_pkg/src/hdl/axi4_pkg.vhd
+ 1
− 1
View file @ 5854f55e
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2020.2 -- Tool version: 2020.2
-- Description: AXI4 format bus signals. -- Description: AXI4 format bus signals.
-- --
-- Last update: 2020-11-25 -- Last update: 2021-05-18
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
......
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