Update scalp_safe_firmware and create scalp_user_firmware.

designs/vivado/scalp_safe_firmware/2020.2/src/hdl/scalp_safe_firmware.vhd

@@ -15,7 +15,7 @@
 -- Tool version: 2020.2
 -- Description: scalp_firmware
 --
--- Last update: 2021-01-18
+-- Last update: 2021-03-12
 --
 ---------------------------------------------------------------------------------
 
@@ -291,6 +291,14 @@ architecture arch of scalp_safe_firmware is
     -- Zynq Reg Bank
     signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
     signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
+    -- RGB Leds
+    signal Led12V5RxS     : std_ulogic                                         := '0';
+    signal Led12V5GxS     : std_ulogic                                         := '0';
+    signal Led12V5BxS     : std_ulogic                                         := '0';
+    signal Led22V5RxS     : std_ulogic                                         := '0';
+    signal Led22V5GxS     : std_ulogic                                         := '0';
+    signal Led22V5BxS     : std_ulogic                                         := '0';
+
 
     -- Attributes
     attribute mark_debug         : string;
@@ -352,6 +360,19 @@ begin
     ProgrammableLogicxB : block is
     begin  -- block ProgrammableLogicxB        
 
+        EntityIOxB : block is
+        begin
+
+            Led12V5RxAS : Led12V5RxSO <= Led12V5RxS;
+            Led12V5GxAS : Led12V5GxSO <= Led12V5GxS;
+            Led12V5BxAS : Led12V5BxSO <= Led12V5BxS;
+            Led22V5RxAS : Led22V5RxSO <= Led22V5RxS;
+            Led22V5GxAS : Led22V5GxSO <= Led22V5GxS;
+            Led22V5BxAS : Led22V5BxSO <= Led22V5BxS;
+
+        end block EntityIOxB;
+
+
         ZynqRegBankxB : block is
         begin  -- block ZynqRegBankxB
 

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Console color print utility
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Text attributes
+set RESET [exec tput sgr0]
+set BOLD [exec tput bold]
+set ITALIC [exec tput sitm]
+set BLINK [exec tput blink]
+set HIGHL [exec tput smso]
+
+# Text colors
+set RED [exec tput setaf 1]
+set GREEN [exec tput setaf 2]
+set YELLOW [exec tput setaf 3]
+set BLUE [exec tput setaf 4]
+set MAGENTA [exec tput setaf 5]
+set CYAN [exec tput setaf 6]
+set WHITE [exec tput setaf 7]
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/clean_prj_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Cleanup project directory
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Cleanup project directory..."
+
+PRJ_DIR=..
+
+# Clean current directory
+rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
+
+# Remove generated project directory
+rm -rf ${PRJ_DIR}/scalp_user_firmware/ 2> /dev/null
+
+# Clean app directory
+rm ${PRJ_DIR}/app/*.h 2> /dev/null
+rm ${PRJ_DIR}/app/*.c 2> /dev/null
+rm ${PRJ_DIR}/app/*.html 2> /dev/null
+
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Create Vivado project..."
+vivado -nojournal -nolog -mode tcl -source create_prj_scalp_user_firmware.tcl -notrace
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/create_prj_scalp_user_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script for re-creating Vivado project 'scalp_user_firmware'
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Include files
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+set PKG_DIR "${PRJ_DIR}/../../../../../packages"
+set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
+
+# Set project type
+set PRJ_TYPE "DESIGN_PRJ_TYPE"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Set the original project directory path for adding/importing sources in the new project
+set src_dir "${PRJ_DIR}/../src"
+set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
+set comp_dir "${ip_dir}/$prj_name"
+set comp_src_dir "${comp_dir}/src"
+set pkg_src_dir "${PKG_DIR}/hw"
+set soc_src_dir "${SOC_DIR}/hw"
+print_status "Set directory paths" "OK"
+
+# Create the project
+create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
+set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
+set_property target_language VHDL [current_project]
+print_status "Create project" "OK"
+
+# Map the IP Repository so that custom IP is included
+set_property ip_repo_paths $ip_dir [current_fileset]
+update_ip_catalog
+
+#----------------------------------------------------------------
+# Add project sources
+#----------------------------------------------------------------
+
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	# add HDL sources
+	set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list    
+	# add the constraints file (XDC)
+	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
+add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_user_firmware.xdc
+	set_property is_enabled true [get_files $src_dir/constrs/scalp_user_firmware.xdc]
+
+	# add IPs source file
+  
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	# components sources are stored in an external directory
+	# add the project component
+	set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
+	set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
+	set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
+	add_files -norecurse $hdl_src_file_list
+	# add IPs source file
+  
+	# add IP-XACT source file
+	#add_files -norecurse $comp_dir/component.xml
+}
+print_status "Add project sources" "OK"
+
+foreach j $vhdl_src_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for project sources" "OK"
+
+#----------------------------------------------------------------
+# Add constraints files
+#----------------------------------------------------------------
+
+
+# Set packages libraries if any
+#set_property library library_name [get_files  $src_dir/hdl/package_name.vhd]
+#update_compile_order -fileset sources_1
+
+# Create the IP Integrator portion of the design
+#create_bd_design "axi_design"
+#update_compile_order -fileset sources_1
+
+# launch the TCL script to generate the IPI design
+source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
+print_status "Add IPI design" "OK"
+
+# Set the top level design
+set_property top $prj_name [current_fileset]
+update_compile_order -fileset sources_1
+
+# Add testbench sources
+if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $src_dir/sim *.v]
+} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
+	set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
+	set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
+}
+set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
+add_files -fileset sim_1 -norecurse $hdl_sim_file_list
+update_compile_order -fileset sim_1
+print_status "Add testbench sources" "OK"
+
+foreach j $vhdl_sim_file_list {
+    set_property file_type {VHDL 2008} [get_files  $j]
+    print_status "VHDL 2008 mode configured for the file $j" "OK"
+}
+print_status "VHDL 2008 mode configured for testbench sources" "OK"
+
+# Add packages sources
+	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
+	add_files -norecurse $vhdl_pkg_file_list
+	foreach j $vhdl_pkg_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+print_status "Add packages sources" "OK"
+print_status "VHDL 2008 mode configured for packages sources" "OK"
+
+# Add SoC wrapper sources files
+	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
+	add_files -norecurse $vhdl_soc_file_list
+	foreach j $vhdl_soc_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
+print_status "Add SoC wrapper sources" "OK"
+print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time to the screen
+puts $start_time
+puts $end_time
+
+exit

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Export the hardware design to SDK"
+
+vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_user_firmware.tcl -notrace
+
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/export_hw_scalp_user_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Export the hardware design to SDK
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+
+# Initialize workspace directories name
+set prj_name "scalp_user_firmware"
+set impl_dir "${PRJ_DIR}/${prj_name}/${prj_name}.runs/impl_1/"
+set export_dir "${PRJ_DIR}/${prj_name}/${prj_name}.sdk"
+print_status "Initialize workspace directories name" "OK"
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+print_status "Open project $prj_name" "OK"
+
+# export the hardware
+file mkdir $export_dir
+file copy -force $impl_dir/$prj_name.sysdef $export_dir/$prj_name.hdf
+print_status "Export hardware to SDK" "OK"
+
+exit
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./gen_bitstream_scalp_user_firmware.tcl -notrace
+
+echo "> Copy bitstream file in current directory..."
+mkdir -p ${PRJ_DIR}/bitstream/
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.runs/impl_1/scalp_user_firmware.bit ${PRJ_DIR}/bitstream/scalp_user_firmware.bit
+
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_user_firmware.tcl

+#!/usr/bin/tcl
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+# Create a variable to store the start time
+set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Open the project
+open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
+update_compile_order -fileset sources_1
+print_status "Open project $prj_name" "OK"
+
+# Run synthesis
+print_status "Run synthesis" "IN_PROGRESS"
+launch_runs synth_1
+wait_on_run synth_1
+print_status "Run synthesis" "OK"
+
+# Run implementation
+print_status "Run implementation" "IN_PROGRESS"
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+wait_on_run impl_1
+print_status "Run implementation" "OK"
+
+# Set the completion time
+set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
+
+# Display the start and end time on the screen
+puts $start_time
+puts $end_time
+
+exit

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Generate software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+PRJ_DIR=..
+
+echo "> Generate software applications..."
+xsdk -batch -source ./gen_sw_apps_scalp_user_firmware.tcl -notrace
+
+echo "> Copy application file in current directory..."
+mkdir -p ${PRJ_DIR}/app/
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_app/Debug/scalp_user_firmware_app.elf ${PRJ_DIR}/app/scalp_user_firmware_app.elf
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_hw_platform_0/system.hdf ${PRJ_DIR}/app/scalp_user_firmware.hdf
+cp ${PRJ_DIR}/scalp_user_firmware/scalp_user_firmware.sdk/scalp_user_firmware_hw_platform_0/ps7_init.tcl ${PRJ_DIR}/app/ps7_init.tcl
+
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_user_firmware.tcl

+#!/usr/bin/tcl
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to generate software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+set workspace_dir "${PRJ_DIR}/$prj_name/$prj_name.sdk/"
+set hw_spec_file "$prj_name.hdf"
+
+set hw_platform_name "${prj_name}_hw_platform_0"
+set proc_name "ps7_cortexa9_0"
+set os_name "freertos823_xilinx"
+
+set bsp_name "${prj_name}_bsp"
+set app_name "${prj_name}_app"
+
+# Set the SDK workspace
+setws $workspace_dir
+print_status "Set workspace directory" "OK"
+
+# Create the hardware project
+sdk createhw -name $hw_platform_name -hwspec $workspace_dir/$hw_spec_file
+print_status "Create hardware project" "OK"
+
+# Create the FreeRTOS BSP
+sdk createbsp -name $bsp_name -hwproject $hw_platform_name -proc $proc_name -os $os_name
+print_status "Create FreeRTOS BSP project" "OK"
+
+# Create the empty application
+sdk createapp -name $app_name -hwproject $hw_platform_name -proc $proc_name -lang C -app {Empty Application} -os $os_name -bsp $bsp_name
+print_status "Create Empty Application project" "OK"
+
+# Import source files
+sdk importsources -name $app_name -path ${PRJ_DIR}/../src/sw/ -linker-script
+print_status "Import project source files" "OK"
+
+# Set the include directories
+configapp -app $app_name include-path "${PRJ_DIR}/../src/inc/"
+configapp -app $app_name include-path "${PRJ_DIR}/../src/lib/"
+configapp -app $app_name include-path "${PRJ_DIR}/../src/mod/"
+print_status "Set includes directories" "OK"
+
+# Build the projects
+print_status "Build BSP project" "IN_PROGRESS"
+sdk projects -build -type bsp -name $bsp_name
+print_status "Build BSP project" "OK"
+
+print_status "Build application project" "IN_PROGRESS"
+sdk projects -build -type app -name $app_name
+print_status "Build application project" "OK"
+
+exit

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load bitstream file
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Load bitstream file..."
+vivado -nojournal -nolog -mode tcl -source ./load_bitstream_scalp_user_firmware.tcl -notrace
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_user_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load FPGA bitstream
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+
+# Open the hardware manager and connect to the hardware server
+open_hw
+print_status "Open hardware manager" "OK"
+connect_hw_server -url localhost:3121
+print_status "Connect to hardware server" "OK"
+
+# Get the hardware target and open it
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
+set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
+open_hw_target
+print_status "Open hardware target" "OK"
+
+# Display targets list
+set index -1
+set targets [lindex [get_hw_devices]]
+puts "Found target(s):"
+foreach target $targets {
+  incr index
+  puts "$index : $target"
+}
+puts "Which target do you want to program?"
+set sel_target [read stdin 1]
+
+# Set the program file
+set_property PROGRAM.FILE ${PRJ_DIR}/bitstream/$prj_name.bit [lindex [get_hw_devices] $sel_target]
+current_hw_device [lindex [get_hw_devices] $sel_target]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] $sel_target]
+print_status "Set program file" "OK"
+
+# Program the device
+print_status "Program device" "IN_PROGRESS"
+program_hw_device [lindex [get_hw_devices] $sel_target]
+print_status "Program device" "OK"
+
+exit

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Load software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Load software application..."
+xsdk -batch -source ./load_sw_app_scalp_user_firmware.tcl -notrace
+echo "> Done"
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/load_sw_app_scalp_user_firmware.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script used to load software application
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+source utils.tcl
+
+set PRJ_DIR ".."
+set prj_name "scalp_user_firmware"
+set hw_platform_name "${prj_name}_hw_platform_0"
+set app_name "${prj_name}_app"
+
+# Connect to the hardware server
+connect -url tcp:127.0.0.1:3121
+print_status "Connect to hardware server" "OK"
+
+# Connect to the processor
+targets 2
+print_status "Connect to ARM Cortex-A9 MPCore #0" "OK"
+
+# Load the hardware design
+loadhw -hw ${PRJ_DIR}/app/$prj_name.hdf
+print_status "Load hardware design" "OK"
+
+# Reset the processor
+rst -processor
+print_status "Reset ARM Cortex-A9 MPCore #0" "OK"
+
+# Initialize the MPSoC
+source ${PRJ_DIR}/app/ps7_init.tcl
+ps7_init
+ps7_post_config
+print_status "Initialize PS7" "OK"
+
+# Load the application
+dow ${PRJ_DIR}/app/$app_name.elf
+print_status "Load software application" "OK"
+
+# Run the application
+con
+print_status "Run software application" "OK"
+
+# Disconnect from the target
+disconnect
+print_status "Disconnect from hardware server" "OK"
+
+exit
+

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/open_prj_scalp_user_firmware.sh

+#!/bin/sh
+
+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Create Vivado project
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+echo "> Open Vivado GUI..."
+vivado -nojournal -nolog -notrace ../scalp_user_firmware/scalp_user_firmware.xpr

designs/vivado/scalp_user_firmware/2020.2/lin64/.scripts/utils.tcl

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: Project management utilities
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# findFiles
+# basedir - the directory to start looking in
+# pattern - A pattern, as defined by the glob command, that the files must match
+proc findFiles { basedir pattern } {
+
+    # Fix the directory name, this ensures the directory name is in the
+    # native format for the platform and contains a final directory seperator
+    set basedir [string trimright [file join [file normalize $basedir] { }]]
+    set fileList {}
+
+    # Look in the current directory for matching files, -type {f r}
+    # means ony readable normal files are looked at, -nocomplain stops
+    # an error being thrown if the returned list is empty
+    foreach fileName [glob -nocomplain -type {f r} -path $basedir $pattern] {
+        lappend fileList $fileName
+    }
+
+    # Now look for any sub direcories in the current directory
+    foreach dirName [glob -nocomplain -type {d  r} -path $basedir *] {
+        # Recusively call the routine on the sub directory and append any
+        # new files to the results
+        set subDirList [findFiles $dirName $pattern]
+        if { [llength $subDirList] > 0 } {
+            foreach subDirFile $subDirList {
+                lappend fileList $subDirFile
+            }
+        }
+    }
+    return $fileList
+}
+
+
+# Print a progress status
+# str The string describing the current status
+# status The status as a string (eg. "OK", "FAILED")
+proc print_status {str status} {
+    set MAX_STR_LENGTH 70
+    source .prompt_colors.tcl
+    puts "${CYAN}>${YELLOW} $str [string repeat " " [expr {$MAX_STR_LENGTH - [string length $str]}]]\[${GREEN}${status}${YELLOW}\]${RESET}"
+}
+

designs/vivado/scalp_user_firmware/2020.2/lin64/setup.sh

+##################################################################################
+#                                 _             _
+#                                | |_  ___ _ __(_)__ _
+#                                | ' \/ -_) '_ \ / _` |
+#                                |_||_\___| .__/_\__,_|
+#                                         |_|
+#
+##################################################################################
+#
+# Company: hepia
+# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
+#
+# Project Name: scalp_user_firmware
+# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
+# Tool version: 2020.2
+# Description: TCL script creating aliases for Vivado project management scripts
+#
+# Last update: 2021-03-17 07:44:47
+#
+##################################################################################
+
+# Create aliases
+alias create_project='cd .scripts && ./create_prj_scalp_user_firmware.sh && cd ..'
+alias clean_project='cd .scripts && ./clean_prj_scalp_user_firmware.sh && cd ..'
+alias export_hw='cd .scripts && ./export_hw_scalp_user_firmware.sh && cd ..'
+alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_user_firmware.sh && cd ..'
+alias load_bitstream='cd .scripts && ./load_bitstream_scalp_user_firmware.sh && cd ..'
+alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_user_firmware.sh && cd ..'
+alias load_sw_app='cd .scripts && ./load_sw_app_scalp_user_firmware.sh && cd ..'
+alias open_gui='cd .scripts && ./open_prj_scalp_user_firmware.sh && cd ..'