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Commit f79b7279 authored by joachim.schmidt's avatar joachim.schmidt
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Update Double Fifo Register

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designs/vivado/scalp_firmware/2020.2/lin64/.gitignore 0 → 100644
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− 0
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##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Git ignore file
#
# Last update: 2021-05-17 08:38:48
#
##################################################################################
# Ignore generated project directory
scalp_firmware
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/.prompt_colors.tcl
+ 24
− 14
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......@@ -15,23 +15,33 @@
# Tool version: 2020.2
# Description: Console color print utility
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
# Try to set a variable with an execution command
# If the command fails, set the variable to an empty string
# cmd - The command to be executed
# return The variable to be set
proc try_setexec {cmd} {
set code [catch { set var [exec {*}$cmd] } ]
if { $code != 0 } { set var "" }
return ${var}
}
# Text attributes
set RESET [exec tput sgr0]
set BOLD [exec tput bold]
set ITALIC [exec tput sitm]
set BLINK [exec tput blink]
set HIGHL [exec tput smso]
set RESET [try_setexec "tput sgr0"]
set BOLD [try_setexec "tput bold"]
set ITALIC [try_setexec "tput sitm"]
set BLINK [try_setexec "tput blink"]
set HIGHL [try_setexec "tput smso"]
# Text colors
set RED [exec tput setaf 1]
set GREEN [exec tput setaf 2]
set YELLOW [exec tput setaf 3]
set BLUE [exec tput setaf 4]
set MAGENTA [exec tput setaf 5]
set CYAN [exec tput setaf 6]
set WHITE [exec tput setaf 7]
set RED [try_setexec "tput setaf 1"]
set GREEN [try_setexec "tput setaf 2"]
set YELLOW [try_setexec "tput setaf 3"]
set BLUE [try_setexec "tput setaf 4"]
set MAGENTA [try_setexec "tput setaf 5"]
set CYAN [try_setexec "tput setaf 6"]
set WHITE [try_setexec "tput setaf 7"]
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+ 1
− 6
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......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Cleanup project directory
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......@@ -31,10 +31,5 @@ rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_firmware/ 2> /dev/null
# Clean app directory
rm ${PRJ_DIR}/app/*.h 2> /dev/null
rm ${PRJ_DIR}/app/*.c 2> /dev/null
rm ${PRJ_DIR}/app/*.html 2> /dev/null
echo "> Done"
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.sh
+ 1
− 1
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......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Create Vivado project
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+ 77
− 57
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......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_firmware'
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......@@ -36,6 +36,7 @@ set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw"
......@@ -49,19 +50,44 @@ set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths $ip_dir [current_fileset]
set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
# Get HDL source files directory
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add HDL sources
set vhdl_src_file_list [findFiles $src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
set hdl_src_dir "${src_dir}/hdl"
set sim_src_dir "${src_dir}/sim"
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
set hdl_src_dir "${comp_src_dir}/hdl"
set sim_src_dir "${comp_src_dir}/sim"
}
# add HDL source files
set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
set verilog_src_file_list [findFiles $hdl_src_dir *.v]
set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
if {$hdl_src_file_list != ""} {
add_files -norecurse $hdl_src_file_list
} else {
print_status "No sources to be added" "WARNING"
}
# Set VHDL version
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Add constraint files and IPs source files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
......@@ -72,7 +98,7 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]
# add IPs source file
# add IPs source files
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_packet_fifo_wrapper/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
......@@ -80,6 +106,13 @@ add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_rx_link_layer/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
}
set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_router/src/hdl *.vhd]
add_files -norecurse $vhdl_ips_file_list
foreach j $vhdl_ips_file_list {
......@@ -102,7 +135,6 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.v
set_property is_enabled true [get_files $j]
}
read_ip ${ip_dir}/scalp_packet_fifo_wrapper/src/ip_core/scalp_packet_fifo/scalp_packet_fifo.xci
read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_user_resets/vio_user_resets.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
......@@ -112,32 +144,16 @@ set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.v
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/west_channel/west_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy/src/ip_core/east_channel/east_channel.xci
read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
read_ip ${ip_dir}/scalp_design_aurora_clk/src/ip_core/scalp_aurora_clk/scalp_aurora_clk.xci
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
# add the project component
set vhdl_src_file_list [findFiles $comp_src_dir/hdl *.vhd]
set verilog_src_file_list [findFiles $comp_src_dir/hdl *.v]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list]
add_files -norecurse $hdl_src_file_list
# add IPs source file
# add IPs source files
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
#----------------------------------------------------------------
# Add constraints files
#----------------------------------------------------------------
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
......@@ -154,24 +170,25 @@ print_status "Add IPI design" "OK"
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add testbench sources
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $src_dir/sim *.v]
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
set vhdl_sim_file_list [findFiles $comp_src_dir/sim *.vhd]
set verilog_sim_file_list [findFiles $comp_src_dir/sim *.v]
}
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list]
# Add simulation sources
set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
set verilog_sim_file_list [findFiles $sim_src_dir *.v]
set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
if {$hdl_sim_file_list != ""} {
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add testbench sources" "OK"
print_status "Add simulation sources" "OK"
} else {
print_status "No simulation sources to be added" "WARNING"
}
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for testbench sources" "OK"
print_status "VHDL 2008 mode configured for simulation sources" "OK"
# Add packages sources
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
......@@ -180,6 +197,7 @@ print_status "VHDL 2008 mode configured for testbench sources" "OK"
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
set_property library xil_defaultlib [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
......@@ -187,6 +205,7 @@ print_status "VHDL 2008 mode configured for testbench sources" "OK"
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
set_property library xil_defaultlib [get_files $j]
}
set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
add_files -norecurse $vhdl_pkg_file_list
......@@ -194,6 +213,7 @@ print_status "VHDL 2008 mode configured for testbench sources" "OK"
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
set_property is_enabled true [get_files $j]
set_property library xil_defaultlib [get_files $j]
}
print_status "Add packages sources" "OK"
print_status "VHDL 2008 mode configured for packages sources" "OK"
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.sh
+ 2
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......@@ -17,11 +17,11 @@
# Tool version: 2020.2
# Description: Export the hardware design to SDK
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
echo "> Export the hardware design to SDK"
echo "> Export the hardware design to Vitis SDK"
vivado -nojournal -nolog -mode tcl -source ./export_hw_scalp_firmware.tcl -notrace
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+ 12
− 11
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......@@ -13,30 +13,31 @@
# Project Name: scalp_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Export the hardware design to SDK
# Description: Export the hardware design to Vitis SDK
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
source utils.tcl
# Project paths
set PRJ_DIR ".."
set SRC_DIR "${PRJ_DIR}/../src"
set EXPORT_DIR "${SRC_DIR}/sw/hw_export"
# Initialize workspace directories name
set prj_name "scalp_firmware"
set impl_dir "${PRJ_DIR}/${prj_name}/${prj_name}.runs/impl_1/"
set export_dir "${PRJ_DIR}/${prj_name}/${prj_name}.sdk"
print_status "Initialize workspace directories name" "OK"
# Create the export directory if not present
file mkdir ${EXPORT_DIR}
print_status "Initialize workspace directories" "OK"
# Open the project
open_project -verbose ${PRJ_DIR}/$prj_name/$prj_name.xpr
open_project -verbose ${PRJ_DIR}/${prj_name}/${prj_name}.xpr
print_status "Open project $prj_name" "OK"
# export the hardware
file mkdir $export_dir
file copy -force $impl_dir/$prj_name.sysdef $export_dir/$prj_name.hdf
print_status "Export hardware to SDK" "OK"
# Export the hardware including the bitstream
write_hw_platform -fixed -force -include_bit -file ${EXPORT_DIR}/${prj_name}.xsa
print_status "Export hardware to Vitis SDK" "OK"
exit
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+ 1
− 1
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......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Generate bitstream file
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+ 1
− 1
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......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: TCL script used to generate bitstream file
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl deleted 100644 → 0
+ 0
− 74
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#!/usr/bin/tcl
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
#
# Project Name: scalp_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: TCL script used to generate software application
#
# Last update: 2021-01-15 09:27:32
#
##################################################################################
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_firmware"
set workspace_dir "${PRJ_DIR}/$prj_name/$prj_name.sdk/"
set hw_spec_file "$prj_name.hdf"
set hw_platform_name "${prj_name}_hw_platform_0"
set proc_name "ps7_cortexa9_0"
set os_name "freertos823_xilinx"
set bsp_name "${prj_name}_bsp"
set app_name "${prj_name}_app"
# Set the SDK workspace
setws $workspace_dir
print_status "Set workspace directory" "OK"
# Create the hardware project
sdk createhw -name $hw_platform_name -hwspec $workspace_dir/$hw_spec_file
print_status "Create hardware project" "OK"
# Create the FreeRTOS BSP
sdk createbsp -name $bsp_name -hwproject $hw_platform_name -proc $proc_name -os $os_name
print_status "Create FreeRTOS BSP project" "OK"
# Create the empty application
sdk createapp -name $app_name -hwproject $hw_platform_name -proc $proc_name -lang C -app {Empty Application} -os $os_name -bsp $bsp_name
print_status "Create Empty Application project" "OK"
# Import source files
sdk importsources -name $app_name -path ${PRJ_DIR}/../src/sw/ -linker-script
print_status "Import project source files" "OK"
# Set the include directories
configapp -app $app_name include-path "${PRJ_DIR}/../src/inc/"
configapp -app $app_name include-path "${PRJ_DIR}/../src/lib/"
configapp -app $app_name include-path "${PRJ_DIR}/../src/mod/"
print_status "Set includes directories" "OK"
# Build the projects
print_status "Build BSP project" "IN_PROGRESS"
sdk projects -build -type bsp -name $bsp_name
print_status "Build BSP project" "OK"
print_status "Build application project" "IN_PROGRESS"
sdk projects -build -type app -name $app_name
print_status "Build application project" "OK"
exit
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+ 1
− 1
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......@@ -17,7 +17,7 @@
# Tool version: 2020.2
# Description: Load bitstream file
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+ 1
− 1
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......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script used to load FPGA bitstream
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/open_prj_scalp_firmware.sh
+ 2
− 2
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......@@ -15,9 +15,9 @@
# Project Name: scalp_firmware
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Create Vivado project
# Description: Open Vivado project GUI
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/utils.tcl
+ 1
− 1
View file @ f79b7279
......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: Project management utilities
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......
designs/vivado/scalp_firmware/2020.2/lin64/.scripts/vivado_pid24324.str 0 → 100644
+ 3890
− 0
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Source diff could not be displayed: it is too large. Options to address this: view the blob.
designs/vivado/scalp_firmware/2020.2/lin64/setup.sh
+ 1
− 3
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......@@ -15,7 +15,7 @@
# Tool version: 2020.2
# Description: TCL script creating aliases for Vivado project management scripts
#
# Last update: 2021-01-15 09:27:32
# Last update: 2021-05-17 08:38:48
#
##################################################################################
......@@ -25,6 +25,4 @@ alias clean_project='cd .scripts && ./clean_prj_scalp_firmware.sh && cd ..'
alias export_hw='cd .scripts && ./export_hw_scalp_firmware.sh && cd ..'
alias gen_bitstream='cd .scripts && ./gen_bitstream_scalp_firmware.sh && cd ..'
alias load_bitstream='cd .scripts && ./load_bitstream_scalp_firmware.sh && cd ..'
alias gen_sw_apps='cd .scripts && ./gen_sw_apps_scalp_firmware.sh && cd ..'
alias load_sw_app='cd .scripts && ./load_sw_app_scalp_firmware.sh && cd ..'
alias open_gui='cd .scripts && ./open_prj_scalp_firmware.sh && cd ..'
designs/vivado/scalp_firmware/2020.2/src/constrs/scalp_firmware.xdc
+ 1
− 0
View file @ f79b7279
......@@ -251,3 +251,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
designs/vivado/scalp_firmware/2020.2/src/constrs/timing_constraints.xdc
+ 1
− 0
View file @ f79b7279
......@@ -31,3 +31,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
designs/vivado/scalp_firmware/2020.2/src/hdl/scalp_firmware.vhd
+ 66
− 68
View file @ f79b7279
......@@ -15,7 +15,7 @@
-- Tool version: 2020.2
-- Description: scalp_firmware
--
-- Last update: 2021-05-10
-- Last update: 2021-05-17
--
---------------------------------------------------------------------------------
......@@ -526,47 +526,26 @@ architecture arch of scalp_firmware is
attribute keep of AuroraClkSlavexC : signal is "true";
attribute keep of AuroraClkMasterxC : signal is "true";
-- Scalp Router
attribute mark_debug of RXAxism2sVectorxD : signal is "true";
attribute keep of RXAxism2sVectorxD : signal is "true";
attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
attribute keep of RXAxiss2mVectorxD : signal is "true";
attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
attribute keep of TXAxiss2mVectorxD : signal is "true";
attribute mark_debug of TXAxism2sVectorxD : signal is "true";
attribute keep of TXAxism2sVectorxD : signal is "true";
-- Scalp Aurora PHY Ready -> TX Side
-- attribute mark_debug of NorthTXM2SxD : signal is "true";
-- attribute keep of NorthTXM2SxD : signal is "true";
-- attribute mark_debug of NorthTXS2MxD : signal is "true";
-- attribute keep of NorthTXS2MxD : signal is "true";
attribute mark_debug of EastTXM2SxD : signal is "true";
attribute keep of EastTXM2SxD : signal is "true";
attribute mark_debug of EastTXS2MxD : signal is "true";
attribute keep of EastTXS2MxD : signal is "true";
-- attribute mark_debug of SouthTXM2SxD : signal is "true";
-- attribute keep of SouthTXM2SxD : signal is "true";
-- attribute mark_debug of SouthTXS2MxD : signal is "true";
-- attribute keep of SouthTXS2MxD : signal is "true";
-- attribute mark_debug of WestTXM2SxD : signal is "true";
-- attribute keep of WestTXM2SxD : signal is "true";
-- attribute mark_debug of WestTXS2MxD : signal is "true";
-- attribute keep of WestTXS2MxD : signal is "true";
-- attribute mark_debug of NorthRXM2SxD : signal is "true";
-- attribute keep of NorthRXM2SxD : signal is "true";
-- attribute mark_debug of NorthRXS2MxD : signal is "true";
-- attribute keep of NorthRXS2MxD : signal is "true";
-- attribute mark_debug of EastRXM2SxD : signal is "true";
-- attribute keep of EastRXM2SxD : signal is "true";
-- attribute mark_debug of EastRXS2MxD : signal is "true";
-- attribute keep of EastRXS2MxD : signal is "true";
-- attribute mark_debug of SouthRXM2SxD : signal is "true";
-- attribute keep of SouthRXM2SxD : signal is "true";
-- attribute mark_debug of SouthRXS2MxD : signal is "true";
-- attribute keep of SouthRXS2MxD : signal is "true";
-- attribute mark_debug of WestRXM2SxD : signal is "true";
-- attribute keep of WestRXM2SxD : signal is "true";
-- attribute mark_debug of WestRXS2MxD : signal is "true";
-- attribute keep of WestRXS2MxD : signal is "true";
-- attribute mark_debug of RXAxism2sVectorxD : signal is "true";
-- attribute keep of RXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of RXAxiss2mVectorxD : signal is "true";
-- attribute keep of RXAxiss2mVectorxD : signal is "true";
-- attribute mark_debug of TXAxism2sVectorxD : signal is "true";
-- attribute keep of TXAxism2sVectorxD : signal is "true";
-- attribute mark_debug of TXAxiss2mVectorxD : signal is "true";
-- attribute keep of TXAxiss2mVectorxD : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
-- attribute mark_debug of : signal is "true";
-- attribute keep of : signal is "true";
begin
......@@ -915,11 +894,14 @@ begin
signal WrSPStatexDP : t_write_sp_states := E_WR_SP_IDLE_0;
signal WrSPStatexDN : t_write_sp_states := E_WR_SP_IDLE_0;
signal VioWrSpValidxS : std_ulogic := '0';
--
signal RXSideLLxDP : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
signal RXSideLLxDN : t_scalp_rx_link_layer_states := E_SCALP_RX_LINK_LAYER_IDLE;
-- Scalp Packet
-- attribute mark_debug of ScalpPacket0xD : signal is "true";
-- attribute keep of ScalpPacket0xD : signal is "true";
attribute mark_debug of ScalpPacketValid12xS : signal is "true";
attribute keep of ScalpPacketValid12xS : signal is "true";
-- attribute mark_debug of ScalpPacketValid12xS : signal is "true";
-- attribute keep of ScalpPacketValid12xS : signal is "true";
-- VIO
-- attribute mark_debug of VioWrSpValidxS : signal is "true";
-- attribute keep of VioWrSpValidxS : signal is "true";
......@@ -1072,6 +1054,9 @@ begin
-- end block ScalpRouterReadyxB;
-- Local Router Net Addr
LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_210;
-- TX Side
NorthTXM2SxAS : NorthTXM2SxD <= TXAxism2sVectorxD(C_NORTH_IF_ID);
EastTXM2SxAS : EastTXM2SxD <= TXAxism2sVectorxD(C_EAST_IF_ID);
SouthTXM2SxAS : SouthTXM2SxD <= TXAxism2sVectorxD(C_SOUTH_IF_ID);
......@@ -1080,6 +1065,7 @@ begin
EastTXS2MxAS : TXAxiss2mVectorxD(C_EAST_IF_ID) <= EastTXS2MxD;
SouthTXS2MxAS : TXAxiss2mVectorxD(C_SOUTH_IF_ID) <= SouthTXS2MxD;
WestTXS2MxAS : TXAxiss2mVectorxD(C_WEST_IF_ID) <= WestTXS2MxD;
-- RX Side
NorthRXM2SxAS : RXAxism2sVectorxD(C_NORTH_IF_ID) <= NorthRXM2SxD;
EastRXM2SxAS : RXAxism2sVectorxD(C_EAST_IF_ID) <= EastRXM2SxD;
SouthRXM2SxAS : RXAxism2sVectorxD(C_SOUTH_IF_ID) <= SouthRXM2SxD;
......@@ -1088,10 +1074,35 @@ begin
EastRXS2MxAS : EastRXS2MxD <= RXAxiss2mVectorxD(C_EAST_IF_ID);
SouthRXS2MxAS : SouthRXS2MxD <= RXAxiss2mVectorxD(C_SOUTH_IF_ID);
WestRXS2MxAS : WestRXS2MxD <= RXAxiss2mVectorxD(C_WEST_IF_ID);
-- Local Router Net Addr
LocNetAddrxAS : LocNetAddrxD <= C_SCALP_PACKET_NET_ADDR_110;
-- Local Ready
-- RXAxiss2mVectorxD(C_LOCAL_IF_ID) <=
-- RXLinkLayerRegxP: process (AuroraClkMasterxC.UserClkxC,
-- ScalpRouterResetxRNA) is
-- begin -- process RXLinkLayerRegxP
-- if ScalpRouterResetxRNA = '0' then
-- RXSideLLxDP <= E_SCALP_RX_LINK_LAYER_IDLE;
-- elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
-- RXSideLLxDP <= RXSideLLxDN;
-- end if;
-- end process RXLinkLayerRegxP;
-- RXLinkLayerxP: process is
-- begin -- process RXLinkLayerxP
-- RXSideLLxDN <= RXSideLLxDP;
-- case RXSideLLxDP is
-- when E_SCALP_RX_LINK_LAYER_IDLE => ;
-- when E_SCALP_RX_LINK_LAYER_WAIT_ON_LAST => ;
-- when E_SCALP_RX_LINK_LAYER_WAIT => ;
-- when others => null;
-- end case;
-- end process RXLinkLayerxP;
WrSpValidxI : entity work.vio_axi_cnt_ctrl
port map (
......@@ -1124,30 +1135,17 @@ begin
TXAxiss2mVectorxDI => TXAxiss2mVectorxD,
QoSVectorxDI => QoSVectorxD);
ReadLocalxP : process (AuroraClkMasterxC.UserClkxC,
ScalpRouterResetxRNA) is
begin -- process ReadLocalxP
if ScalpRouterResetxRNA = '0' then
TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '0';
elsif rising_edge(AuroraClkMasterxC.UserClkxC) then
TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '1';
-- if TXAxism2sVectorxD(C_LOCAL_IF_ID).ValidxS = '1' then
-- TXAxiss2mVectorxD(C_LOCAL_IF_ID).ReadyxS <= '1';
-- end if;
end if;
end process ReadLocalxP;
-- ScalpAxis2SPxI : entity work.scalp_axis_to_sp
-- generic map (
-- C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
-- C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
-- port map (
-- SysClkxCI => AuroraClkMasterxC.UserClkxC,
-- SysRstxRNAI => ScalpRouterResetxRNA,
-- ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
-- ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
-- ScalpPacketxDO => ScalpPacketLocalxD,
-- ScalpPacketValidxSO => ScalpPacketValidLocalxS);
ScalpAxis2SPxI : entity work.scalp_axis_to_sp
generic map (
C_SCALP_PACKET_PAYLOAD_SIZE => C_SCALP_PACKET_PAYLOAD_SIZE,
C_SCALP_RANDOM_READY => C_SCALP_RANDOM_READY)
port map (
SysClkxCI => AuroraClkMasterxC.UserClkxC,
SysRstxRNAI => ScalpRouterResetxRNA,
ScalpAxism2sxDI => TXAxism2sVectorxD(C_LOCAL_IF_ID),
ScalpAxiss2mxDO => TXAxiss2mVectorxD(C_LOCAL_IF_ID),
ScalpPacketxDO => ScalpPacketLocalxD,
ScalpPacketValidxSO => ScalpPacketValidLocalxS);
WritePacketxB : block is
begin -- block WritePacketxB
......
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