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Commit f9b74c88 authored by joachim.schmidt's avatar joachim.schmidt
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Update scalp_safe_firmware and scalp_user_firmware.

parent c03cd99e
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with 2199 additions and 51 deletions
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 12 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 12 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdValidxS]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
...@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small ...@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
...@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO] ...@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2020.2 -- Tool version: 2020.2
-- Description: scalp_firmware -- Description: scalp_firmware
-- --
-- Last update: 2021-03-12 -- Last update: 2021-03-22
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -298,7 +298,11 @@ architecture arch of scalp_safe_firmware is ...@@ -298,7 +298,11 @@ architecture arch of scalp_safe_firmware is
signal Led22V5RxS : std_ulogic := '0'; signal Led22V5RxS : std_ulogic := '0';
signal Led22V5GxS : std_ulogic := '0'; signal Led22V5GxS : std_ulogic := '0';
signal Led22V5BxS : std_ulogic := '0'; signal Led22V5BxS : std_ulogic := '0';
-- RgbLeds Ctrl Port
signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds Enum
type t_rgb_leds is (E_LED1_R, E_LED1_G, E_LED1_B, E_LED2_R, E_LED2_G, E_LED2_B);
-- Attributes -- Attributes
attribute mark_debug : string; attribute mark_debug : string;
...@@ -353,7 +357,8 @@ begin ...@@ -353,7 +357,8 @@ begin
RdValidxSO => RdValidxS, RdValidxSO => RdValidxS,
WrAddrxDO => WrAddrxD, WrAddrxDO => WrAddrxD,
WrDataxDO => WrDataxD, WrDataxDO => WrDataxD,
WrValidxSO => WrValidxS); WrValidxSO => WrValidxS,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
end block ProcessingSystemxB; end block ProcessingSystemxB;
...@@ -363,12 +368,12 @@ begin ...@@ -363,12 +368,12 @@ begin
EntityIOxB : block is EntityIOxB : block is
begin begin
Led12V5RxAS : Led12V5RxSO <= Led12V5RxS; Led12V5RxAS : Led12V5RxSO <= RgbLedsCtrlPortxD(0);
Led12V5GxAS : Led12V5GxSO <= Led12V5GxS; Led12V5GxAS : Led12V5GxSO <= RgbLedsCtrlPortxD(1);
Led12V5BxAS : Led12V5BxSO <= Led12V5BxS; Led12V5BxAS : Led12V5BxSO <= RgbLedsCtrlPortxD(2);
Led22V5RxAS : Led22V5RxSO <= Led22V5RxS; Led22V5RxAS : Led22V5RxSO <= RgbLedsCtrlPortxD(3);
Led22V5GxAS : Led22V5GxSO <= Led22V5GxS; Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
Led22V5BxAS : Led22V5BxSO <= Led22V5BxS; Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
end block EntityIOxB; end block EntityIOxB;
......
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/processing_system7_0/inst/FCLK_CLK0]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrDataxD[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 12 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdAddrxD[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 12 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrAddrxD[11]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RgbLedsCtrlPortxDP[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[0]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[1]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[2]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[3]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[4]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[5]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[6]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[7]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[8]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[9]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[10]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[11]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[12]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[13]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[14]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[15]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[16]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[17]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[18]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[19]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[20]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[21]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[22]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[23]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[24]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[25]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[26]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[27]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[28]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[29]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[30]} {ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdDataxD[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/RdValidxS]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list ProcessingSystemxB.ZynqxI/ScalpZynqPSxI/scalp_safe_firmware_0/U0/WrValidxS]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
...@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small ...@@ -250,3 +250,4 @@ set_operating_conditions -airflow 0 -heatsink none -board small
...@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO] ...@@ -30,3 +30,4 @@ create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
-- Tool version: 2020.2 -- Tool version: 2020.2
-- Description: scalp_user_firmware -- Description: scalp_user_firmware
-- --
-- Last update: 2021-03-17 -- Last update: 2021-03-24
-- --
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -291,12 +291,7 @@ architecture arch of scalp_user_firmware is ...@@ -291,12 +291,7 @@ architecture arch of scalp_user_firmware is
signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); signal CtrlRegPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0'); signal CtrlRegPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
-- RGB Leds -- RGB Leds
signal Led12V5RxS : std_ulogic := '0'; signal RgbLedsCtrlPortxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal Led12V5GxS : std_ulogic := '0';
signal Led12V5BxS : std_ulogic := '0';
signal Led22V5RxS : std_ulogic := '0';
signal Led22V5GxS : std_ulogic := '0';
signal Led22V5BxS : std_ulogic := '0';
-- Attributes -- Attributes
...@@ -352,7 +347,8 @@ begin ...@@ -352,7 +347,8 @@ begin
RdValidxSO => RdValidxS, RdValidxSO => RdValidxS,
WrAddrxDO => WrAddrxD, WrAddrxDO => WrAddrxD,
WrDataxDO => WrDataxD, WrDataxDO => WrDataxD,
WrValidxSO => WrValidxS); WrValidxSO => WrValidxS,
RgbLedsCtrlPortxDO => RgbLedsCtrlPortxD);
end block ProcessingSystemxB; end block ProcessingSystemxB;
...@@ -362,12 +358,12 @@ begin ...@@ -362,12 +358,12 @@ begin
EntityIOxB : block is EntityIOxB : block is
begin begin
Led12V5RxAS : Led12V5RxSO <= Led12V5RxS; Led12V5RxAS : Led12V5RxSO <= RgbLedsCtrlPortxD(0);
Led12V5GxAS : Led12V5GxSO <= Led12V5GxS; Led12V5GxAS : Led12V5GxSO <= RgbLedsCtrlPortxD(1);
Led12V5BxAS : Led12V5BxSO <= Led12V5BxS; Led12V5BxAS : Led12V5BxSO <= RgbLedsCtrlPortxD(2);
Led22V5RxAS : Led22V5RxSO <= Led22V5RxS; Led22V5RxAS : Led22V5RxSO <= RgbLedsCtrlPortxD(3);
Led22V5GxAS : Led22V5GxSO <= Led22V5GxS; Led22V5GxAS : Led22V5GxSO <= RgbLedsCtrlPortxD(4);
Led22V5BxAS : Led22V5BxSO <= Led22V5BxS; Led22V5BxAS : Led22V5BxSO <= RgbLedsCtrlPortxD(5);
end block EntityIOxB; end block EntityIOxB;
......
<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>hepia.ch</spirit:vendor>
<spirit:library>user</spirit:library>
<spirit:name>scalp_safe_firmware_reg_bank</spirit:name>
<spirit:version>1.3</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>SAXILitexDIO</spirit:name>
<spirit:displayName>SAXILitexDIO</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="SAXILitexDIO"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiRReadyxSI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiBValidxSO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiBReadyxSI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiAWValidxSI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiAWReadyxSO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiWDataxDI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiRRespxDO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiRValidxSO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiARAddrxDI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiARReadyxSO</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>SAxiAWAddrxDI</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
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<xilinx:packagingInfo>
<xilinx:xilinxVersion>2020.2</xilinx:xilinxVersion>
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</spirit:vendorExtensions>
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
entity scalp_safe_firmware_reg_bank is
generic (
C_AXI4_ARADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_RDATA_SIZE : integer range 0 to 32 := 32;
C_AXI4_RRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_AWADDR_SIZE : integer range 0 to 32 := 32;
C_AXI4_WDATA_SIZE : integer range 0 to 32 := 32;
C_AXI4_WSTRB_SIZE : integer range 0 to 4 := 4;
C_AXI4_BRESP_SIZE : integer range 0 to 2 := 2;
C_AXI4_ADDR_SIZE : integer range 0 to 32 := 12;
C_AXI4_DATA_SIZE : integer range 0 to 32 := 32);
port (
-- Clock and reset
SAxiClkxCI : in std_ulogic;
SAxiRstxRANI : in std_ulogic;
-- AXI4 Lite
-- Read Channel
-- Read Address Channel
SAxiARAddrxDI : in std_ulogic_vector((C_AXI4_ARADDR_SIZE - 1) downto 0);
SAxiARValidxSI : in std_ulogic;
SAxiARReadyxSO : out std_ulogic;
-- Read Data Channel
SAxiRDataxDO : out std_ulogic_vector((C_AXI4_RDATA_SIZE - 1) downto 0);
SAxiRRespxDO : out std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0);
SAxiRValidxSO : out std_ulogic;
SAxiRReadyxSI : in std_ulogic;
-- Write Channel
-- Write Address Channel
SAxiAWAddrxDI : in std_ulogic_vector((C_AXI4_AWADDR_SIZE - 1) downto 0);
SAxiAWValidxSI : in std_ulogic;
SAxiAWReadyxSO : out std_ulogic;
-- Write Data Channel
SAxiWDataxDI : in std_ulogic_vector((C_AXI4_WDATA_SIZE - 1) downto 0);
SAxiWStrbxDI : in std_ulogic_vector((C_AXI4_WSTRB_SIZE - 1) downto 0);
SAxiWValidxSI : in std_ulogic;
SAxiWReadyxSO : out std_ulogic;
-- Write Response Channel
SAxiBRespxDO : out std_ulogic_vector((C_AXI4_BRESP_SIZE - 1) downto 0);
SAxiBValidxSO : out std_ulogic;
SAxiBReadyxSI : in std_ulogic;
-- Register Access IO
RgbLedsCtrlPortxDO : out std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0));
end scalp_safe_firmware_reg_bank;
architecture behavioral of scalp_safe_firmware_reg_bank is
-- Constants
constant C_AXI4_RRESP_OKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_RRESP_EXOKAY : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_RRESP_SLVERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_RRESP_DECERR : std_ulogic_vector((C_AXI4_RRESP_SIZE - 1) downto 0) := "11";
constant C_AXI4_BRESP_OKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "00";
constant C_AXI4_BRESP_EXOKAY : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "01";
constant C_AXI4_BRESP_SLVERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "10";
constant C_AXI4_BRESP_DECERR : std_logic_vector((C_AXI4_BRESP_SIZE - 1) downto 0) := "11";
-- Signals
-- Clock and reset
signal SAxiClkxC : std_ulogic := '0';
signal SAxiRstxRAN : std_ulogic := '0';
-- AXI4 Lite
signal SAxiARReadyxS : std_ulogic := '0';
signal SAxiRValidxS : std_ulogic := '0';
signal SAxiBValidxS : std_ulogic := '0';
signal SAxiWReadyxS : std_ulogic := '0';
signal SAxiAWReadyxS : std_ulogic := '0';
signal WrAddrxDN : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrAddrxDP : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
-- Signals of access to the register bank
signal RdAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal RdDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal RdValidxS : std_ulogic := '0';
signal WrAddrxD : std_ulogic_vector((C_AXI4_ADDR_SIZE - 1) downto 0) := (others => '0');
signal WrDataxD : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := (others => '0');
signal WrValidxS : std_ulogic := '0';
-- Registers list
signal RgbLedsCtrlPortxDN : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
signal RgbLedsCtrlPortxDP : std_ulogic_vector((C_AXI4_DATA_SIZE - 1) downto 0) := x"00000000";
-- Attributes
attribute mark_debug : string;
attribute keep : string;
--
attribute mark_debug of RdAddrxD : signal is "true";
attribute keep of RdAddrxD : signal is "true";
attribute mark_debug of RdDataxD : signal is "true";
attribute keep of RdDataxD : signal is "true";
attribute mark_debug of RdValidxS : signal is "true";
attribute keep of RdValidxS : signal is "true";
attribute mark_debug of WrAddrxD : signal is "true";
attribute keep of WrAddrxD : signal is "true";
attribute mark_debug of WrDataxD : signal is "true";
attribute keep of WrDataxD : signal is "true";
attribute mark_debug of WrValidxS : signal is "true";
attribute keep of WrValidxS : signal is "true";
attribute mark_debug of RgbLedsCtrlPortxDP : signal is "true";
attribute keep of RgbLedsCtrlPortxDP : signal is "true";
begin
assert C_AXI4_RDATA_SIZE = C_AXI4_DATA_SIZE
report "RDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_ARADDR_SIZE >= C_AXI4_ADDR_SIZE
report "ARADDR and ADDR vectors must be the same" severity failure;
assert C_AXI4_WDATA_SIZE = C_AXI4_DATA_SIZE
report "WDATA and DATA vectors must be the same" severity failure;
assert C_AXI4_AWADDR_SIZE >= C_AXI4_ADDR_SIZE
report "AWADDR and ADDR vectors must be the same" severity failure;
EntityIOxB : block is
begin -- block EntityIOxB
-- Clock and reset
SAxiClkxAS : SAxiClkxC <= SAxiClkxCI;
SAxiRstxAS : SAxiRstxRAN <= SAxiRstxRANI;
-- Read Channel
SAxiARReadyxAS : SAxiARReadyxSO <= SAxiARReadyxS;
SAxiRValidxAS : SAxiRValidxSO <= SAxiRValidxS;
SAxiRDataxAS : SAxiRDataxDO <= RdDataxD;
RdValidxAS : RdValidxS <= SAxiARValidxSI;
RdAddrxAS : RdAddrxD((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiARAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0);
SAxiRRespxAS : SAxiRRespxDO <= C_AXI4_RRESP_OKAY;
-- Write Channel
SAxiBRespxAS : SAxiBRespxDO <= C_AXI4_BRESP_OKAY;
SAxiBValidxAS : SAxiBValidxSO <= SAxiBValidxS;
SAxiWReadyxAS : SAxiWReadyxSO <= SAxiWReadyxS;
SAxiAWReadyxAS : SAxiAWReadyxSO <= SAxiAWReadyxS;
WrValidxAS : WrValidxS <= SAxiWValidxSI;
WrDataxAS : WrDataxD <= SAxiWDataxDI;
WrAddrOutxAS : WrAddrxD <= WrAddrxDP;
WrAddrxAS : WrAddrxDN((C_AXI4_ADDR_SIZE - 1) downto 0) <= SAxiAWAddrxDI((C_AXI4_ADDR_SIZE - 1) downto 0) when
SAxiAWValidxSI = '1' else
WrAddrxDP((C_AXI4_ADDR_SIZE - 1) downto 0);
RgbLedsCtrlPortxAS : RgbLedsCtrlPortxDO <= RgbLedsCtrlPortxDP;
end block EntityIOxB;
AXI4LitexB : block is
begin -- block AXI4LitexB
ReadChannelxB : block is
begin -- block ReadChannelxB
ReadAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process ReadAddrChanxP
if SAxiRstxRAN = '0' then
SAxiARReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiARReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiARReadyxS <= SAxiARReadyxS;
end if;
if SAxiARValidxSI = '1' then
SAxiARReadyxS <= '0';
end if;
if SAxiARReadyxS <= '0' and SAxiRReadyxSI = '1' then
SAxiARReadyxS <= '1';
end if;
end if;
end process ReadAddrChanxP;
ReadDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadDataChanxP
if SAxiRstxRAN = '0' then
SAxiRValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiRValidxS <= SAxiRValidxS;
if SAxiARValidxSI = '1' and SAxiARReadyxS = '1' then
SAxiRValidxS <= '1';
end if;
if SAxiRValidxS = '1' and SAxiRReadyxSI = '1' then
SAxiRValidxS <= '0';
end if;
end if;
end process ReadDataChanxP;
end block ReadChannelxB;
WriteChannelxB : block is
begin --block WriteChannelxB
WrAddrRegxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WrAddrRegxP
if SAxiRstxRAN = '0' then
WrAddrxDP <= (others => '0');
elsif rising_edge(SAxiClkxC) then
WrAddrxDP <= WrAddrxDN;
end if;
end process WrAddrRegxP;
WriteAddrChanxP : process (SAxiClkxC, SAxiRstxRAN) is
variable StateAfterResetxS : boolean := true;
begin -- process WriteAddrChanxP
if SAxiRstxRAN = '0' then
SAxiAWReadyxS <= '0';
StateAfterResetxS := true;
elsif rising_edge(SAxiClkxC) then
if StateAfterResetxS = true then
SAxiAWReadyxS <= '1';
StateAfterResetxS := false;
else
SAxiAWReadyxS <= SAxiAWReadyxS;
end if;
if SAxiAWValidxSI = '1' then
SAxiAWReadyxS <= '0';
end if;
if SAxiWValidxSI = '1' then
SAxiAWReadyxS <= '1';
end if;
end if;
end process WriteAddrChanxP;
WriteDataChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteDataChanxP
if SAxiRstxRAN = '0' then
SAxiWReadyxS <= '0';
elsif rising_edge(SAxiClkxCI) then
SAxiWReadyxS <= SAxiWReadyxS;
if SAxiAWValidxSI = '1' and SAxiAWReadyxS = '1' then
SAxiWReadyxS <= '1';
end if;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiWReadyxS <= '0';
end if;
end if;
end process WriteDataChanxP;
WriteRespChanxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process WriteRespChanxP
if SAxiRstxRAN = '0' then
SAxiBValidxS <= '0';
elsif rising_edge(SAxiClkxC) then
SAxiBValidxS <= SAxiBValidxS;
if SAxiWValidxSI = '1' and SAxiWReadyxS = '1' then
SAxiBValidxS <= '1';
end if;
if SAxiBValidxS = '1' and SAxiBReadyxSI = '1' then
SAxiBValidxS <= '0';
end if;
end if;
end process WriteRespChanxP;
end block WriteChannelxB;
end block AXI4LitexB;
ScalpSafeFirmwareRegBankxB : block is
begin -- block ScalpSafeFirmwareRegBankxB
WriteRegPortxP : process (WrAddrxD, WrDataxD, WrValidxS,
RgbLedsCtrlPortxDP) is
begin -- process WriteRegPortxP
RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP;
if WrValidxS = '1' then
case WrAddrxD is
when x"000" => RgbLedsCtrlPortxDN <= WrDataxD;
when x"004" => RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP or WrDataxD;
when x"008" => RgbLedsCtrlPortxDN <= RgbLedsCtrlPortxDP and not WrDataxD;
when others => null;
end case;
end if;
end process WriteRegPortxP;
ReadRegPortxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process ReadRegPortxP
if SAxiRstxRAN = '0' then
RdDataxD <= (others => '0');
elsif rising_edge(SAxiClkxC) then
RdDataxD <= (others => '0');
if RdValidxS = '1' then
case RdAddrxD is
when x"000" => RdDataxD <= RgbLedsCtrlPortxDP;
when others => RdDataxD <= (others => '0');
end case;
end if;
end if;
end process ReadRegPortxP;
UpdateRegBankxP : process (SAxiClkxC, SAxiRstxRAN) is
begin -- process UpdateRegBankxP
if SAxiRstxRAN = '0' then
RgbLedsCtrlPortxDP <= x"00000000";
elsif rising_edge(SAxiClkxC) then
RgbLedsCtrlPortxDP <= RgbLedsCtrlPortxDN;
end if;
end process UpdateRegBankxP;
end block ScalpSafeFirmwareRegBankxB;
end behavioral;
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch
--
-- Module Name: tb_scalp_safe_firmware_reg_bank - arch
-- Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
-- Tool version: 2020.2
-- Description: Testbench for scalp_safe_firmware_reg_bank
--
-- Last update: 2021-03-22 08:20:36
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_scalp_safe_firmware_reg_bank is
end tb_scalp_safe_firmware_reg_bank;
architecture behavioral of tb_scalp_safe_firmware_reg_bank is
begin
end behavioral;
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "C_AXI4_ADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_ARADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_AWADDR_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_BRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_DATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_RRESP_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WDATA_SIZE" -parent ${Page_0}
ipgui::add_param $IPINST -name "C_AXI4_WSTRB_SIZE" -parent ${Page_0}
}
proc update_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to update C_AXI4_ADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ADDR_SIZE { PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to validate C_AXI4_ADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to update C_AXI4_ARADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_ARADDR_SIZE { PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to validate C_AXI4_ARADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to update C_AXI4_AWADDR_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_AWADDR_SIZE { PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to validate C_AXI4_AWADDR_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to update C_AXI4_BRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_BRESP_SIZE { PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to validate C_AXI4_BRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to update C_AXI4_DATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_DATA_SIZE { PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to validate C_AXI4_DATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to update C_AXI4_RDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RDATA_SIZE { PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to validate C_AXI4_RDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to update C_AXI4_RRESP_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_RRESP_SIZE { PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to validate C_AXI4_RRESP_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to update C_AXI4_WDATA_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WDATA_SIZE { PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to validate C_AXI4_WDATA_SIZE
return true
}
proc update_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to update C_AXI4_WSTRB_SIZE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.C_AXI4_WSTRB_SIZE { PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to validate C_AXI4_WSTRB_SIZE
return true
}
proc update_MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE PARAM_VALUE.C_AXI4_ARADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ARADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ARADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RDATA_SIZE { MODELPARAM_VALUE.C_AXI4_RDATA_SIZE PARAM_VALUE.C_AXI4_RDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_RRESP_SIZE { MODELPARAM_VALUE.C_AXI4_RRESP_SIZE PARAM_VALUE.C_AXI4_RRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_RRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_RRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE { MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE PARAM_VALUE.C_AXI4_AWADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_AWADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_AWADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WDATA_SIZE { MODELPARAM_VALUE.C_AXI4_WDATA_SIZE PARAM_VALUE.C_AXI4_WDATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WDATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WDATA_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE { MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE PARAM_VALUE.C_AXI4_WSTRB_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_WSTRB_SIZE}] ${MODELPARAM_VALUE.C_AXI4_WSTRB_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_BRESP_SIZE { MODELPARAM_VALUE.C_AXI4_BRESP_SIZE PARAM_VALUE.C_AXI4_BRESP_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_BRESP_SIZE}] ${MODELPARAM_VALUE.C_AXI4_BRESP_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_ADDR_SIZE { MODELPARAM_VALUE.C_AXI4_ADDR_SIZE PARAM_VALUE.C_AXI4_ADDR_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_ADDR_SIZE}] ${MODELPARAM_VALUE.C_AXI4_ADDR_SIZE}
}
proc update_MODELPARAM_VALUE.C_AXI4_DATA_SIZE { MODELPARAM_VALUE.C_AXI4_DATA_SIZE PARAM_VALUE.C_AXI4_DATA_SIZE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.C_AXI4_DATA_SIZE}] ${MODELPARAM_VALUE.C_AXI4_DATA_SIZE}
}
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_safe_firmware_reg_bank
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Git ignore file
#
# Last update: 2021-03-22 08:20:36
#
##################################################################################
# Ignore generated project directory
scalp_safe_firmware_reg_bank
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_safe_firmware_reg_bank
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Console color print utility
#
# Last update: 2021-03-22 08:20:36
#
##################################################################################
# Try to set a variable with an execution command
# If the command fails, set the variable to an empty string
# cmd - The command to be executed
# return The variable to be set
proc try_setexec {cmd} {
set code [catch { set var [exec {*}$cmd] } ]
if { $code != 0 } { set var "" }
return ${var}
}
# Text attributes
set RESET [try_setexec "tput sgr0"]
set BOLD [try_setexec "tput bold"]
set ITALIC [try_setexec "tput sitm"]
set BLINK [try_setexec "tput blink"]
set HIGHL [try_setexec "tput smso"]
# Text colors
set RED [try_setexec "tput setaf 1"]
set GREEN [try_setexec "tput setaf 2"]
set YELLOW [try_setexec "tput setaf 3"]
set BLUE [try_setexec "tput setaf 4"]
set MAGENTA [try_setexec "tput setaf 5"]
set CYAN [try_setexec "tput setaf 6"]
set WHITE [try_setexec "tput setaf 7"]
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_safe_firmware_reg_bank
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Cleanup project directory
#
# Last update: 2021-03-22 08:20:36
#
##################################################################################
echo "> Cleanup project directory..."
PRJ_DIR=..
# Clean current directory
rm -rf ${PRJ_DIR}/.Xil/ 2> /dev/null
# Remove generated project directory
rm -rf ${PRJ_DIR}/scalp_safe_firmware_reg_bank/ 2> /dev/null
echo "> Done"
#!/bin/sh
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_safe_firmware_reg_bank
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: Create Vivado project
#
# Last update: 2021-03-22 08:20:36
#
##################################################################################
echo "> Create Vivado project..."
vivado -nojournal -nolog -mode tcl -source create_prj_scalp_safe_firmware_reg_bank.tcl -notrace
echo "> Done"
##################################################################################
# _ _
# | |_ ___ _ __(_)__ _
# | ' \/ -_) '_ \ / _` |
# |_||_\___| .__/_\__,_|
# |_|
#
##################################################################################
#
# Company: hepia
# Author: Joachim Schmidt <joachim.schmidt@hesge.ch
#
# Project Name: scalp_safe_firmware_reg_bank
# Target Device: hepia-cores.ch:scalp_node:part0:0.1 xc7z015clg485-2
# Tool version: 2020.2
# Description: TCL script for re-creating Vivado project 'scalp_safe_firmware_reg_bank'
#
# Last update: 2021-03-22 08:20:36
#
##################################################################################
# Include files
source utils.tcl
set PRJ_DIR ".."
set prj_name "scalp_safe_firmware_reg_bank"
set PKG_DIR "${PRJ_DIR}/../../../../../packages"
set SOC_DIR "${PRJ_DIR}/../../../../../soc/"
# Set project type
set PRJ_TYPE "COMP_PRJ_TYPE"
# Create a variable to store the start time
set start_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Set the original project directory path for adding/importing sources in the new project
set src_dir "${PRJ_DIR}/../src"
set ip_dir "${PRJ_DIR}/../../../../../ips/hw"
set periph_dir "${PRJ_DIR}/../../../../../peripherals/hw"
set comp_dir "${ip_dir}/$prj_name"
set comp_src_dir "${comp_dir}/src"
set pkg_src_dir "${PKG_DIR}/hw"
set soc_src_dir "${SOC_DIR}/hw"
print_status "Set directory paths" "OK"
# Create the project
create_project $prj_name ${PRJ_DIR}/$prj_name -part xc7z015clg485-2
set_property board_part hepia-cores.ch:scalp_node:part0:0.1 [current_project]
set_property target_language VHDL [current_project]
print_status "Create project" "OK"
# Map the IP Repository so that custom IP is included
set_property ip_repo_paths [list $ip_dir $periph_dir] [current_fileset]
update_ip_catalog
#----------------------------------------------------------------
# Add project sources
#----------------------------------------------------------------
# Get HDL source files directory
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
set hdl_src_dir "${src_dir}/hdl"
set sim_src_dir "${src_dir}/sim"
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# components sources are stored in an external directory
set hdl_src_dir "${comp_src_dir}/hdl"
set sim_src_dir "${comp_src_dir}/sim"
}
# add HDL source files
set vhdl_src_file_list [findFiles $hdl_src_dir *.vhd]
set verilog_src_file_list [findFiles $hdl_src_dir *.v]
set system_verilog_src_file_list [findFiles $hdl_src_dir *.sv]
set hdl_src_file_list [list {*}$vhdl_src_file_list {*}$verilog_src_file_list {*}$system_verilog_src_file_list]
if {$hdl_src_file_list != ""} {
add_files -norecurse $hdl_src_file_list
} else {
print_status "No sources to be added" "WARNING"
}
# Set VHDL version
foreach j $vhdl_src_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for project sources" "OK"
# Add constraint files and IPs source files
if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
# add the constraints file (XDC)
add_files -fileset constrs_1 -norecurse $src_dir/constrs/${prj_name}.xdc
set_property is_enabled true [get_files $src_dir/constrs/${prj_name}.xdc]
# add IPs source files
} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
# add IPs source files
# add IP-XACT source file
#add_files -norecurse $comp_dir/component.xml
}
print_status "Add project sources" "OK"
# Set packages libraries if any
#set_property library library_name [get_files $src_dir/hdl/package_name.vhd]
#update_compile_order -fileset sources_1
# Create the IP Integrator portion of the design
#create_bd_design "axi_design"
#update_compile_order -fileset sources_1
# launch the TCL script to generate the IPI design
source $src_dir/ipi_tcl/${prj_name}_ipi.tcl
print_status "Add IPI design" "OK"
# Set the top level design
set_property top $prj_name [current_fileset]
update_compile_order -fileset sources_1
# Add simulation sources
set vhdl_sim_file_list [findFiles $sim_src_dir *.vhd]
set verilog_sim_file_list [findFiles $sim_src_dir *.v]
set system_verilog_sim_file_list [findFiles $sim_src_dir *.sv]
set hdl_sim_file_list [list {*}$vhdl_sim_file_list {*}$verilog_sim_file_list {*}$system_verilog_sim_file_list]
if {$hdl_sim_file_list != ""} {
add_files -fileset sim_1 -norecurse $hdl_sim_file_list
update_compile_order -fileset sim_1
print_status "Add simulation sources" "OK"
} else {
print_status "No simulation sources to be added" "WARNING"
}
foreach j $vhdl_sim_file_list {
set_property file_type {VHDL 2008} [get_files $j]
print_status "VHDL 2008 mode configured for the file $j" "OK"
}
print_status "VHDL 2008 mode configured for simulation sources" "OK"
# Add packages sources
# Add SoC wrapper sources files
# Set the completion time
set end_time [clock format [clock seconds] -format {%b. %d, %Y %I:%M:%S %p}]
# Display the start and end time to the screen
puts $start_time
puts $end_time
exit
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