Add a dummy test bench

Labo1B/tb_test.vhd

+------
+--
+-- Test bench to simulate success and error
+--
+-- Author: Sébastien Gendre
+--
+------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dummy_test is
+end dummy_test;
+
+architecture arch of dummy_test is
+begin
+
+
+  monitor_process: process()
+  begin
+    -- Uncomment the line you want to apply
+    assert false
+      report "Test of error"
+      severity error;
+  end process monitor_process;
+
+  
+end arch;
+