Add a simple dummy test bench

Labo1B/tb_test.vhd

@@ -16,12 +16,15 @@ architecture arch of dummy_test is
 begin
 
 
-  monitor_process: process()
+  monitor_process: process
   begin
     -- Uncomment the line you want to apply
     assert false
       report "Test of error"
       severity error;
+
+    -- Wait endlessly
+    wait;
   end process monitor_process;
 
   

Top/labo1b/list/sim_1.sim

+Labo1B/tb_test.vhd 93 lib=xil_defaultlib

Top/labo1b/sim.conf

 [sim_1]
 ACTIVE=1
-TOP=reg_decalage
+TOP=dummy_test