Updated firmware design "scalp_firmware" with back pressure management for each receiving fifo.

997921ee · joachim.schmidt · 2b34341c · 997921ee · 997921ee · 997921ee
Commit 997921ee authored 4 years ago by joachim.schmidt
--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/clean_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Cleanup project directory
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/create_prj_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script for re-creating Vivado project 'scalp_firmware'
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################

@@ -65,15 +65,21 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 	# add the constraints file (XDC)
 	add_files -fileset constrs_1 -norecurse $src_dir/constrs/debug.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/debug.xdc]
-	add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
+add_files -fileset constrs_1 -norecurse  $src_dir/constrs/ibert_constraints.xdc
 	set_property is_enabled false [get_files $src_dir/constrs/ibert_constraints.xdc]
-	add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/timing_constraints.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/timing_constraints.xdc]
-	add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
+add_files -fileset constrs_1 -norecurse $src_dir/constrs/scalp_firmware.xdc
 	set_property is_enabled true [get_files $src_dir/constrs/scalp_firmware.xdc]

-	#add_files -fileset constrs_1 -norecurse  $src_dir/constrs/${prj_name}.xdc
 	# add IPs source file
+	set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy_rx_fifo/src/hdl *.vhd]
+	add_files -norecurse $vhdl_ips_file_list
+	foreach j $vhdl_ips_file_list {
+		set_property file_type {VHDL 2008} [get_files  $j]
+		print_status "VHDL 2008 mode configured for the file $j" "OK"
+		set_property is_enabled true [get_files $j]
+	}
 	set vhdl_ips_file_list [findFiles ${ip_dir}/scalp_aurora_phy/src/hdl *.vhd]
 	add_files -norecurse $vhdl_ips_file_list
 	foreach j $vhdl_ips_file_list {
@@ -81,6 +87,7 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
+	read_ip ${ip_dir}/scalp_aurora_phy_rx_fifo/src/ip_core/axis_data_fifo/axis_data_fifo.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_status/vio_status.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/data_counter/data_counter.xci
 	read_ip ${ip_dir}/scalp_design_debug/src/ip_core/vio_axi_cnt_ctrl/vio_axi_cnt_ctrl.xci
@@ -153,29 +160,6 @@ foreach j $vhdl_sim_file_list {
 print_status "VHDL 2008 mode configured for testbench sources" "OK"

 # Add packages sources
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
-	add_files -norecurse $vhdl_pkg_file_list
-	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
-		print_status "VHDL 2008 mode configured for the file $j" "OK"
-		set_property is_enabled true [get_files $j]
-	}
-	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_status_pkg/src/hdl *.vhd]
-	add_files -norecurse $vhdl_pkg_file_list
-	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
-		print_status "VHDL 2008 mode configured for the file $j" "OK"
-		set_property is_enabled true [get_files $j]
-	}
-	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/axi4_pkg/src/hdl *.vhd]
-	add_files -norecurse $vhdl_pkg_file_list
-	foreach j $vhdl_pkg_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
-		print_status "VHDL 2008 mode configured for the file $j" "OK"
-		set_property is_enabled true [get_files $j]
-	}
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
 	set vhdl_pkg_file_list [findFiles ${PRJ_DIR}/../../../../../packages/hw/aurora_drp_pkg/src/hdl *.vhd]
 	add_files -norecurse $vhdl_pkg_file_list
 	foreach j $vhdl_pkg_file_list {
@@ -197,20 +181,10 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
-}
 print_status "Add packages sources" "OK"
 print_status "VHDL 2008 mode configured for packages sources" "OK"

 # Add SoC wrapper sources files
-if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
-	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
-	add_files -norecurse $vhdl_soc_file_list
-	foreach j $vhdl_soc_file_list {
-		set_property file_type {VHDL 2008} [get_files  $j]
-		print_status "VHDL 2008 mode configured for the file $j" "OK"
-		set_property is_enabled true [get_files $j]
-	}
-} elseif {$PRJ_TYPE == "COMP_PRJ_TYPE"} {
 	set vhdl_soc_file_list [findFiles ${PRJ_DIR}/../../../../../soc/hw/scalp_zynqps/src/hdl *.vhd]
 	add_files -norecurse $vhdl_soc_file_list
 	foreach j $vhdl_soc_file_list {
@@ -218,7 +192,6 @@ if {$PRJ_TYPE == "DESIGN_PRJ_TYPE"} {
 		print_status "VHDL 2008 mode configured for the file $j" "OK"
 		set_property is_enabled true [get_files $j]
 	}
-}
 print_status "Add SoC wrapper sources" "OK"
 print_status "VHDL 2008 mode configured for SoC wrapper sources" "OK"


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/export_hw_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Export the hardware design to SDK
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate bitstream file
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_bitstream_scalp_firmware.tcl
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate bitstream file
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Generate software application
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/gen_sw_apps_scalp_firmware.tcl
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to generate software application
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load bitstream file
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_bitstream_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load FPGA bitstream
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Load software application
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/load_sw_app_scalp_firmware.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script used to load software application
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/open_prj_scalp_firmware.sh
@@ -17,7 +17,7 @@
 # Tool version: 2019.2
 # Description: Create Vivado project
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/.scripts/utils.tcl
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: Project management utilities
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
+++ b/designs/vivado/scalp_firmware/2019.2/lin64/setup.sh
@@ -15,7 +15,7 @@
 # Tool version: 2019.2
 # Description: TCL script creating aliases for Vivado project management scripts
 #
-# Last update: 2020-10-13 13:10:02
+# Last update: 2020-11-07 09:14:14
 #
 ##################################################################################


--- a/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/hdl/scalp_firmware.vhd
--- a/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
+++ b/designs/vivado/scalp_firmware/2019.2/src/sim/tb_scalp_firmware.vhd
@@ -15,7 +15,7 @@
 -- Tool version: 2019.2
 -- Description: Testbench for scalp_firmware
 --
-- Last update: 2020-10-13 13:10:02
+-- Last update: 2020-11-07 09:14:14
 --
 ---------------------------------------------------------------------------------