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Creation of the constraint files and the top level HDL file.
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- designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc 158 additions, 0 deletions...vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc
- designs/vivado/scalp_router_firmware/2020.2/src/constrs/ibert_constraints.xdc 382 additions, 0 deletions..._router_firmware/2020.2/src/constrs/ibert_constraints.xdc
- designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc 256 additions, 0 deletions...alp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc
- designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc 36 additions, 0 deletions...router_firmware/2020.2/src/constrs/timing_constraints.xdc
- designs/vivado/scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd 68 additions, 0 deletions.../scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd
- designs/vivado/scalp_router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd 1354 additions, 1 deletion..._router_firmware/2020.2/src/hdl/scalp_router_firmware.vhd
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