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Commit 218bad77 authored by joachim.schmidt's avatar joachim.schmidt
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Creation of the constraint files and the top level HDL file.

parent 034332ca
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designs/vivado/scalp_router_firmware/2020.2/src/constrs/debug.xdc 0 → 100644
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− 0
View file @ 218bad77
create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/ScalpAuroraPhyxB.ScalpAuroraPhyWrapperxI/ClkRstxB.AuroraClockModulexI/CLK]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {TXAxism2sVectorxD[1][DataxD][31]} {TXAxism2sVectorxD[1][DataxD][30]} {TXAxism2sVectorxD[1][DataxD][29]} {TXAxism2sVectorxD[1][DataxD][28]} {TXAxism2sVectorxD[1][DataxD][27]} {TXAxism2sVectorxD[1][DataxD][26]} {TXAxism2sVectorxD[1][DataxD][25]} {TXAxism2sVectorxD[1][DataxD][24]} {TXAxism2sVectorxD[1][DataxD][23]} {TXAxism2sVectorxD[1][DataxD][22]} {TXAxism2sVectorxD[1][DataxD][21]} {TXAxism2sVectorxD[1][DataxD][20]} {TXAxism2sVectorxD[1][DataxD][19]} {TXAxism2sVectorxD[1][DataxD][18]} {TXAxism2sVectorxD[1][DataxD][17]} {TXAxism2sVectorxD[1][DataxD][16]} {TXAxism2sVectorxD[1][DataxD][15]} {TXAxism2sVectorxD[1][DataxD][14]} {TXAxism2sVectorxD[1][DataxD][13]} {TXAxism2sVectorxD[1][DataxD][12]} {TXAxism2sVectorxD[1][DataxD][11]} {TXAxism2sVectorxD[1][DataxD][10]} {TXAxism2sVectorxD[1][DataxD][9]} {TXAxism2sVectorxD[1][DataxD][8]} {TXAxism2sVectorxD[1][DataxD][7]} {TXAxism2sVectorxD[1][DataxD][6]} {TXAxism2sVectorxD[1][DataxD][5]} {TXAxism2sVectorxD[1][DataxD][4]} {TXAxism2sVectorxD[1][DataxD][3]} {TXAxism2sVectorxD[1][DataxD][2]} {TXAxism2sVectorxD[1][DataxD][1]} {TXAxism2sVectorxD[1][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {TXAxism2sVectorxD[2][DataxD][31]} {TXAxism2sVectorxD[2][DataxD][30]} {TXAxism2sVectorxD[2][DataxD][29]} {TXAxism2sVectorxD[2][DataxD][28]} {TXAxism2sVectorxD[2][DataxD][27]} {TXAxism2sVectorxD[2][DataxD][26]} {TXAxism2sVectorxD[2][DataxD][25]} {TXAxism2sVectorxD[2][DataxD][24]} {TXAxism2sVectorxD[2][DataxD][23]} {TXAxism2sVectorxD[2][DataxD][22]} {TXAxism2sVectorxD[2][DataxD][21]} {TXAxism2sVectorxD[2][DataxD][20]} {TXAxism2sVectorxD[2][DataxD][19]} {TXAxism2sVectorxD[2][DataxD][18]} {TXAxism2sVectorxD[2][DataxD][17]} {TXAxism2sVectorxD[2][DataxD][16]} {TXAxism2sVectorxD[2][DataxD][15]} {TXAxism2sVectorxD[2][DataxD][14]} {TXAxism2sVectorxD[2][DataxD][13]} {TXAxism2sVectorxD[2][DataxD][12]} {TXAxism2sVectorxD[2][DataxD][11]} {TXAxism2sVectorxD[2][DataxD][10]} {TXAxism2sVectorxD[2][DataxD][9]} {TXAxism2sVectorxD[2][DataxD][8]} {TXAxism2sVectorxD[2][DataxD][7]} {TXAxism2sVectorxD[2][DataxD][6]} {TXAxism2sVectorxD[2][DataxD][5]} {TXAxism2sVectorxD[2][DataxD][4]} {TXAxism2sVectorxD[2][DataxD][3]} {TXAxism2sVectorxD[2][DataxD][2]} {TXAxism2sVectorxD[2][DataxD][1]} {TXAxism2sVectorxD[2][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {TXAxism2sVectorxD[0][DataxD][31]} {TXAxism2sVectorxD[0][DataxD][30]} {TXAxism2sVectorxD[0][DataxD][29]} {TXAxism2sVectorxD[0][DataxD][28]} {TXAxism2sVectorxD[0][DataxD][27]} {TXAxism2sVectorxD[0][DataxD][26]} {TXAxism2sVectorxD[0][DataxD][25]} {TXAxism2sVectorxD[0][DataxD][24]} {TXAxism2sVectorxD[0][DataxD][23]} {TXAxism2sVectorxD[0][DataxD][22]} {TXAxism2sVectorxD[0][DataxD][21]} {TXAxism2sVectorxD[0][DataxD][20]} {TXAxism2sVectorxD[0][DataxD][19]} {TXAxism2sVectorxD[0][DataxD][18]} {TXAxism2sVectorxD[0][DataxD][17]} {TXAxism2sVectorxD[0][DataxD][16]} {TXAxism2sVectorxD[0][DataxD][15]} {TXAxism2sVectorxD[0][DataxD][14]} {TXAxism2sVectorxD[0][DataxD][13]} {TXAxism2sVectorxD[0][DataxD][12]} {TXAxism2sVectorxD[0][DataxD][11]} {TXAxism2sVectorxD[0][DataxD][10]} {TXAxism2sVectorxD[0][DataxD][9]} {TXAxism2sVectorxD[0][DataxD][8]} {TXAxism2sVectorxD[0][DataxD][7]} {TXAxism2sVectorxD[0][DataxD][6]} {TXAxism2sVectorxD[0][DataxD][5]} {TXAxism2sVectorxD[0][DataxD][4]} {TXAxism2sVectorxD[0][DataxD][3]} {TXAxism2sVectorxD[0][DataxD][2]} {TXAxism2sVectorxD[0][DataxD][1]} {TXAxism2sVectorxD[0][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {TXAxism2sVectorxD[3][DataxD][31]} {TXAxism2sVectorxD[3][DataxD][30]} {TXAxism2sVectorxD[3][DataxD][29]} {TXAxism2sVectorxD[3][DataxD][28]} {TXAxism2sVectorxD[3][DataxD][27]} {TXAxism2sVectorxD[3][DataxD][26]} {TXAxism2sVectorxD[3][DataxD][25]} {TXAxism2sVectorxD[3][DataxD][24]} {TXAxism2sVectorxD[3][DataxD][23]} {TXAxism2sVectorxD[3][DataxD][22]} {TXAxism2sVectorxD[3][DataxD][21]} {TXAxism2sVectorxD[3][DataxD][20]} {TXAxism2sVectorxD[3][DataxD][19]} {TXAxism2sVectorxD[3][DataxD][18]} {TXAxism2sVectorxD[3][DataxD][17]} {TXAxism2sVectorxD[3][DataxD][16]} {TXAxism2sVectorxD[3][DataxD][15]} {TXAxism2sVectorxD[3][DataxD][14]} {TXAxism2sVectorxD[3][DataxD][13]} {TXAxism2sVectorxD[3][DataxD][12]} {TXAxism2sVectorxD[3][DataxD][11]} {TXAxism2sVectorxD[3][DataxD][10]} {TXAxism2sVectorxD[3][DataxD][9]} {TXAxism2sVectorxD[3][DataxD][8]} {TXAxism2sVectorxD[3][DataxD][7]} {TXAxism2sVectorxD[3][DataxD][6]} {TXAxism2sVectorxD[3][DataxD][5]} {TXAxism2sVectorxD[3][DataxD][4]} {TXAxism2sVectorxD[3][DataxD][3]} {TXAxism2sVectorxD[3][DataxD][2]} {TXAxism2sVectorxD[3][DataxD][1]} {TXAxism2sVectorxD[3][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {TXAxism2sVectorxD[4][DataxD][31]} {TXAxism2sVectorxD[4][DataxD][30]} {TXAxism2sVectorxD[4][DataxD][29]} {TXAxism2sVectorxD[4][DataxD][28]} {TXAxism2sVectorxD[4][DataxD][27]} {TXAxism2sVectorxD[4][DataxD][26]} {TXAxism2sVectorxD[4][DataxD][25]} {TXAxism2sVectorxD[4][DataxD][24]} {TXAxism2sVectorxD[4][DataxD][23]} {TXAxism2sVectorxD[4][DataxD][22]} {TXAxism2sVectorxD[4][DataxD][21]} {TXAxism2sVectorxD[4][DataxD][20]} {TXAxism2sVectorxD[4][DataxD][19]} {TXAxism2sVectorxD[4][DataxD][18]} {TXAxism2sVectorxD[4][DataxD][17]} {TXAxism2sVectorxD[4][DataxD][16]} {TXAxism2sVectorxD[4][DataxD][15]} {TXAxism2sVectorxD[4][DataxD][14]} {TXAxism2sVectorxD[4][DataxD][13]} {TXAxism2sVectorxD[4][DataxD][12]} {TXAxism2sVectorxD[4][DataxD][11]} {TXAxism2sVectorxD[4][DataxD][10]} {TXAxism2sVectorxD[4][DataxD][9]} {TXAxism2sVectorxD[4][DataxD][8]} {TXAxism2sVectorxD[4][DataxD][7]} {TXAxism2sVectorxD[4][DataxD][6]} {TXAxism2sVectorxD[4][DataxD][5]} {TXAxism2sVectorxD[4][DataxD][4]} {TXAxism2sVectorxD[4][DataxD][3]} {TXAxism2sVectorxD[4][DataxD][2]} {TXAxism2sVectorxD[4][DataxD][1]} {TXAxism2sVectorxD[4][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property port_width 32 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {TXAxism2sVectorxD[5][DataxD][31]} {TXAxism2sVectorxD[5][DataxD][30]} {TXAxism2sVectorxD[5][DataxD][29]} {TXAxism2sVectorxD[5][DataxD][28]} {TXAxism2sVectorxD[5][DataxD][27]} {TXAxism2sVectorxD[5][DataxD][26]} {TXAxism2sVectorxD[5][DataxD][25]} {TXAxism2sVectorxD[5][DataxD][24]} {TXAxism2sVectorxD[5][DataxD][23]} {TXAxism2sVectorxD[5][DataxD][22]} {TXAxism2sVectorxD[5][DataxD][21]} {TXAxism2sVectorxD[5][DataxD][20]} {TXAxism2sVectorxD[5][DataxD][19]} {TXAxism2sVectorxD[5][DataxD][18]} {TXAxism2sVectorxD[5][DataxD][17]} {TXAxism2sVectorxD[5][DataxD][16]} {TXAxism2sVectorxD[5][DataxD][15]} {TXAxism2sVectorxD[5][DataxD][14]} {TXAxism2sVectorxD[5][DataxD][13]} {TXAxism2sVectorxD[5][DataxD][12]} {TXAxism2sVectorxD[5][DataxD][11]} {TXAxism2sVectorxD[5][DataxD][10]} {TXAxism2sVectorxD[5][DataxD][9]} {TXAxism2sVectorxD[5][DataxD][8]} {TXAxism2sVectorxD[5][DataxD][7]} {TXAxism2sVectorxD[5][DataxD][6]} {TXAxism2sVectorxD[5][DataxD][5]} {TXAxism2sVectorxD[5][DataxD][4]} {TXAxism2sVectorxD[5][DataxD][3]} {TXAxism2sVectorxD[5][DataxD][2]} {TXAxism2sVectorxD[5][DataxD][1]} {TXAxism2sVectorxD[5][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property port_width 32 [get_debug_ports u_ila_0/probe6]
connect_debug_port u_ila_0/probe6 [get_nets [list {TXAxism2sVectorxD[6][DataxD][31]} {TXAxism2sVectorxD[6][DataxD][30]} {TXAxism2sVectorxD[6][DataxD][29]} {TXAxism2sVectorxD[6][DataxD][28]} {TXAxism2sVectorxD[6][DataxD][27]} {TXAxism2sVectorxD[6][DataxD][26]} {TXAxism2sVectorxD[6][DataxD][25]} {TXAxism2sVectorxD[6][DataxD][24]} {TXAxism2sVectorxD[6][DataxD][23]} {TXAxism2sVectorxD[6][DataxD][22]} {TXAxism2sVectorxD[6][DataxD][21]} {TXAxism2sVectorxD[6][DataxD][20]} {TXAxism2sVectorxD[6][DataxD][19]} {TXAxism2sVectorxD[6][DataxD][18]} {TXAxism2sVectorxD[6][DataxD][17]} {TXAxism2sVectorxD[6][DataxD][16]} {TXAxism2sVectorxD[6][DataxD][15]} {TXAxism2sVectorxD[6][DataxD][14]} {TXAxism2sVectorxD[6][DataxD][13]} {TXAxism2sVectorxD[6][DataxD][12]} {TXAxism2sVectorxD[6][DataxD][11]} {TXAxism2sVectorxD[6][DataxD][10]} {TXAxism2sVectorxD[6][DataxD][9]} {TXAxism2sVectorxD[6][DataxD][8]} {TXAxism2sVectorxD[6][DataxD][7]} {TXAxism2sVectorxD[6][DataxD][6]} {TXAxism2sVectorxD[6][DataxD][5]} {TXAxism2sVectorxD[6][DataxD][4]} {TXAxism2sVectorxD[6][DataxD][3]} {TXAxism2sVectorxD[6][DataxD][2]} {TXAxism2sVectorxD[6][DataxD][1]} {TXAxism2sVectorxD[6][DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
connect_debug_port u_ila_0/probe7 [get_nets [list {WestRXM2SxD[DataxD][31]} {WestRXM2SxD[DataxD][30]} {WestRXM2SxD[DataxD][29]} {WestRXM2SxD[DataxD][28]} {WestRXM2SxD[DataxD][27]} {WestRXM2SxD[DataxD][26]} {WestRXM2SxD[DataxD][25]} {WestRXM2SxD[DataxD][24]} {WestRXM2SxD[DataxD][23]} {WestRXM2SxD[DataxD][22]} {WestRXM2SxD[DataxD][21]} {WestRXM2SxD[DataxD][20]} {WestRXM2SxD[DataxD][19]} {WestRXM2SxD[DataxD][18]} {WestRXM2SxD[DataxD][17]} {WestRXM2SxD[DataxD][16]} {WestRXM2SxD[DataxD][15]} {WestRXM2SxD[DataxD][14]} {WestRXM2SxD[DataxD][13]} {WestRXM2SxD[DataxD][12]} {WestRXM2SxD[DataxD][11]} {WestRXM2SxD[DataxD][10]} {WestRXM2SxD[DataxD][9]} {WestRXM2SxD[DataxD][8]} {WestRXM2SxD[DataxD][7]} {WestRXM2SxD[DataxD][6]} {WestRXM2SxD[DataxD][5]} {WestRXM2SxD[DataxD][4]} {WestRXM2SxD[DataxD][3]} {WestRXM2SxD[DataxD][2]} {WestRXM2SxD[DataxD][1]} {WestRXM2SxD[DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
connect_debug_port u_ila_0/probe8 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][31]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][30]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][29]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][28]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][27]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][26]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][25]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][24]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][23]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][22]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][21]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][20]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][19]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][18]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][17]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][16]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][15]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][14]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][13]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][12]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][11]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][10]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][9]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][8]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][7]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][6]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][5]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][4]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][3]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][2]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][1]} {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[DataxD][0]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
connect_debug_port u_ila_0/probe9 [get_nets [list ScalpPacketValid12xS]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
connect_debug_port u_ila_0/probe10 [get_nets [list {TXAxism2sVectorxD[0][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
connect_debug_port u_ila_0/probe11 [get_nets [list {TXAxism2sVectorxD[0][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
connect_debug_port u_ila_0/probe12 [get_nets [list {TXAxism2sVectorxD[1][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
connect_debug_port u_ila_0/probe13 [get_nets [list {TXAxism2sVectorxD[1][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
connect_debug_port u_ila_0/probe14 [get_nets [list {TXAxism2sVectorxD[2][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
connect_debug_port u_ila_0/probe15 [get_nets [list {TXAxism2sVectorxD[2][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
connect_debug_port u_ila_0/probe16 [get_nets [list {TXAxism2sVectorxD[3][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {TXAxism2sVectorxD[3][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
connect_debug_port u_ila_0/probe18 [get_nets [list {TXAxism2sVectorxD[4][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
connect_debug_port u_ila_0/probe19 [get_nets [list {TXAxism2sVectorxD[4][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
connect_debug_port u_ila_0/probe20 [get_nets [list {TXAxism2sVectorxD[5][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
connect_debug_port u_ila_0/probe21 [get_nets [list {TXAxism2sVectorxD[5][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
connect_debug_port u_ila_0/probe22 [get_nets [list {TXAxism2sVectorxD[6][LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
connect_debug_port u_ila_0/probe23 [get_nets [list {TXAxism2sVectorxD[6][ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
connect_debug_port u_ila_0/probe24 [get_nets [list {TXAxiss2mVectorxD[0][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
connect_debug_port u_ila_0/probe25 [get_nets [list {TXAxiss2mVectorxD[1][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
connect_debug_port u_ila_0/probe26 [get_nets [list {TXAxiss2mVectorxD[2][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
connect_debug_port u_ila_0/probe27 [get_nets [list {TXAxiss2mVectorxD[3][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
connect_debug_port u_ila_0/probe28 [get_nets [list {TXAxiss2mVectorxD[4][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
connect_debug_port u_ila_0/probe29 [get_nets [list {TXAxiss2mVectorxD[5][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
connect_debug_port u_ila_0/probe30 [get_nets [list {TXAxiss2mVectorxD[6][ReadyxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
connect_debug_port u_ila_0/probe31 [get_nets [list {WestRXM2SxD[LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
connect_debug_port u_ila_0/probe32 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[LastxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
connect_debug_port u_ila_0/probe33 [get_nets [list {ProgrammableLogicxB.GTPhyxB.ScalpAuroraPhyxI/WestRXM2SxD[ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
connect_debug_port u_ila_0/probe34 [get_nets [list {WestRXM2SxD[ValidxS]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
connect_debug_port u_ila_0/probe35 [get_nets [list {WestRXS2MxD[ReadyxS]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets PSSysClkxC]
designs/vivado/scalp_router_firmware/2020.2/src/constrs/scalp_firmware.xdc 0 → 100644
+ 256
− 0
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############################################################################
# Programmable Logic placement constraints #
############################################################################
##### USB interface (bank 13) #####
# USB_VBUS_PWRFAULT_i
set_property PACKAGE_PIN AA19 [get_ports UsbVbusPwrFaultxSI]
set_property IOSTANDARD LVCMOS25 [get_ports UsbVbusPwrFaultxSI]
##### PLL interface (banks 35 and 34) #####
# PLL_2V5_CLKuWire_o
set_property PACKAGE_PIN G8 [get_ports Pll2V5ClkuWirexCO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkuWirexCO]
# PLL_2V5_DATAuWire_o
set_property PACKAGE_PIN G7 [get_ports Pll2V5DatauWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5DatauWirexSO]
# PLL_2V5_LEuWire_o
set_property PACKAGE_PIN G6 [get_ports Pll2V5LEuWirexSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LEuWirexSO]
# PLL_2V5_GOE_o
set_property PACKAGE_PIN F6 [get_ports Pll2V5GOExSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5GOExSO]
# PLL_2V5_LD_i
set_property PACKAGE_PIN H6 [get_ports Pll2V5LDxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5LDxSI]
# PLL_2V5_SYNC_n_o
set_property PACKAGE_PIN H5 [get_ports Pll2V5SyncxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5SyncxSO]
# PLL_2V5_CLKIN0_LOS_i (bank 34)
set_property PACKAGE_PIN J3 [get_ports Pll2V5ClkIn0LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn0LOSxSI]
# PLL_2V5_CLKIN1_LOS_i (bank 34)
set_property PACKAGE_PIN K2 [get_ports Pll2V5ClkIn1LOSxSI]
set_property IOSTANDARD LVCMOS25 [get_ports Pll2V5ClkIn1LOSxSI]
##### GTP interfaces (bank 112) #####
set_property PACKAGE_PIN U9 [get_ports GTPRefClk0PxCI]
set_property PACKAGE_PIN V9 [get_ports GTPRefClk0NxCI]
#set_property PACKAGE_PIN "U5" [get_ports "GTPRefClk1PxCI"]
#set_property PACKAGE_PIN "V5" [get_ports "GTPRefClk1NxCI"]
set_property PACKAGE_PIN Y8 [get_ports GTPFromNorthNxSI]
set_property PACKAGE_PIN W8 [get_ports GTPFromNorthPxSI]
set_property PACKAGE_PIN Y4 [get_ports GTPToNorthNxSO]
set_property PACKAGE_PIN W4 [get_ports GTPToNorthPxSO]
set_property PACKAGE_PIN AB7 [get_ports GTPFromSouthNxSI]
set_property PACKAGE_PIN AA7 [get_ports GTPFromSouthPxSI]
set_property PACKAGE_PIN AB3 [get_ports GTPToSouthNxSO]
set_property PACKAGE_PIN AA3 [get_ports GTPToSouthPxSO]
set_property PACKAGE_PIN AB9 [get_ports GTPFromEastNxSI]
set_property PACKAGE_PIN AA9 [get_ports GTPFromEastPxSI]
set_property PACKAGE_PIN AB5 [get_ports GTPToEastNxSO]
set_property PACKAGE_PIN AA5 [get_ports GTPToEastPxSO]
set_property PACKAGE_PIN Y6 [get_ports GTPFromWestNxSI]
set_property PACKAGE_PIN W6 [get_ports GTPFromWestPxSI]
set_property PACKAGE_PIN Y2 [get_ports GTPToWestNxSO]
set_property PACKAGE_PIN W2 [get_ports GTPToWestPxSO]
##### LVDS links towards edge connectors #####
# North (bank 35)
#set_property PACKAGE_PIN "E8" [get_ports "LVDS2V5North7PxSIO"]
#set_property PACKAGE_PIN "D8" [get_ports "LVDS2V5North7NxSIO"]
#set_property PACKAGE_PIN "D7" [get_ports "LVDS2V5North6PxSIO"]
#set_property PACKAGE_PIN "D6" [get_ports "LVDS2V5North6NxSIO"]
#set_property PACKAGE_PIN "C8" [get_ports "LVDS2V5North5PxSIO"]
#set_property PACKAGE_PIN "B8" [get_ports "LVDS2V5North5NxSIO"]
#set_property PACKAGE_PIN "B7" [get_ports "LVDS2V5North4PxSIO"]
#set_property PACKAGE_PIN "B6" [get_ports "LVDS2V5North4NxSIO"]
#set_property PACKAGE_PIN "A7" [get_ports "LVDS2V5North3PxSIO"]
#set_property PACKAGE_PIN "A6" [get_ports "LVDS2V5North3NxSIO"]
#set_property PACKAGE_PIN "A5" [get_ports "LVDS2V5North2PxSIO"]
#set_property PACKAGE_PIN "A4" [get_ports "LVDS2V5North2NxSIO"]
#set_property PACKAGE_PIN "B2" [get_ports "LVDS2V5North1PxSIO"]
#set_property PACKAGE_PIN "B1" [get_ports "LVDS2V5North1NxSIO"]
#set_property PACKAGE_PIN "A2" [get_ports "LVDS2V5North0PxSIO"]
#set_property PACKAGE_PIN "A1" [get_ports "LVDS2V5North0NxSIO"]
# South (bank 13)
#set_property PACKAGE_PIN "V15" [get_ports "LVDS2V5South7PxSIO"]
#set_property PACKAGE_PIN "W15" [get_ports "LVDS2V5South7NxSIO"]
#set_property PACKAGE_PIN "AB13" [get_ports "LVDS2V5South6PxSIO"]
#set_property PACKAGE_PIN "AB14" [get_ports "LVDS2V5South6NxSIO"]
#set_property PACKAGE_PIN "V13" [get_ports "LVDS2V5South5PxSIO"]
#set_property PACKAGE_PIN "V14" [get_ports "LVDS2V5South5NxSIO"]
#set_property PACKAGE_PIN "Y12" [get_ports "LVDS2V5South4PxSIO"]
#set_property PACKAGE_PIN "Y13" [get_ports "LVDS2V5South4NxSIO"]
#set_property PACKAGE_PIN "AA12" [get_ports "LVDS2V5South3PxSIO"]
#set_property PACKAGE_PIN "AB12" [get_ports "LVDS2V5South3NxSIO"]
#set_property PACKAGE_PIN "W12" [get_ports "LVDS2V5South2PxSIO"]
#set_property PACKAGE_PIN "W13" [get_ports "LVDS2V5South2NxSIO"]
#set_property PACKAGE_PIN "AA11" [get_ports "LVDS2V5South1PxSIO"]
#set_property PACKAGE_PIN "AB11" [get_ports "LVDS2V5South1NxSIO"]
#set_property PACKAGE_PIN "V11" [get_ports "LVDS2V5South0PxSIO"]
#set_property PACKAGE_PIN "W11" [get_ports "LVDS2V5South0NxSIO"]
# East (bank 13)
#set_property PACKAGE_PIN "V16" [get_ports "LVDS2V5East7PxSIO"]
#set_property PACKAGE_PIN "W16" [get_ports "LVDS2V5East7NxSIO"]
#set_property PACKAGE_PIN "W17" [get_ports "LVDS2V5East6PxSIO"]
#set_property PACKAGE_PIN "Y17" [get_ports "LVDS2V5East6NxSIO"]
#set_property PACKAGE_PIN "U13" [get_ports "LVDS2V5East5PxSIO"]
#set_property PACKAGE_PIN "U14" [get_ports "LVDS2V5East5NxSIO"]
#set_property PACKAGE_PIN "V18" [get_ports "LVDS2V5East4PxSIO"]
#set_property PACKAGE_PIN "W18" [get_ports "LVDS2V5East4NxSIO"]
#set_property PACKAGE_PIN "U11" [get_ports "LVDS2V5East3PxSIO"]
#set_property PACKAGE_PIN "U12" [get_ports "LVDS2V5East3NxSIO"]
#set_property PACKAGE_PIN "U19" [get_ports "LVDS2V5East2PxSIO"]
#set_property PACKAGE_PIN "V19" [get_ports "LVDS2V5East2NxSIO"]
#set_property PACKAGE_PIN "R17" [get_ports "LVDS2V5East1PxSIO"]
#set_property PACKAGE_PIN "T17" [get_ports "LVDS2V5East1NxSIO"]
#set_property PACKAGE_PIN "U17" [get_ports "LVDS2V5East0PxSIO"]
#set_property PACKAGE_PIN "U18" [get_ports "LVDS2V5East0NxSIO"]
# West (bank 35)
#set_property PACKAGE_PIN "H4" [get_ports "LVDS2V5West7PxSIO"]
#set_property PACKAGE_PIN "H3" [get_ports "LVDS2V5West7NxSIO"]
#set_property PACKAGE_PIN "H1" [get_ports "LVDS2V5West6PxSIO"]
#set_property PACKAGE_PIN "G1" [get_ports "LVDS2V5West6NxSIO"]
#set_property PACKAGE_PIN "G3" [get_ports "LVDS2V5West5PxSIO"]
#set_property PACKAGE_PIN "G2" [get_ports "LVDS2V5West5NxSIO"]
#set_property PACKAGE_PIN "F2" [get_ports "LVDS2V5West4PxSIO"]
#set_property PACKAGE_PIN "F1" [get_ports "LVDS2V5West4NxSIO"]
#set_property PACKAGE_PIN "G4" [get_ports "LVDS2V5West3PxSIO"]
#set_property PACKAGE_PIN "F4" [get_ports "LVDS2V5West3NxSIO"]
#set_property PACKAGE_PIN "E2" [get_ports "LVDS2V5West2PxSIO"]
#set_property PACKAGE_PIN "D2" [get_ports "LVDS2V5West2NxSIO"]
#set_property PACKAGE_PIN "E4" [get_ports "LVDS2V5West1PxSIO"]
#set_property PACKAGE_PIN "E3" [get_ports "LVDS2V5West1NxSIO"]
#set_property PACKAGE_PIN "D1" [get_ports "LVDS2V5West0PxSIO"]
#set_property PACKAGE_PIN "C1" [get_ports "LVDS2V5West0NxSIO"]
##### LVDS links towards top-bottom connectors #####
# Top (bank 34)
#set_property PACKAGE_PIN "J8" [get_ports "LVDS2V5Top7PxSIO"]
#set_property PACKAGE_PIN "K8" [get_ports "LVDS2V5Top7NxSIO"]
#set_property PACKAGE_PIN "K7" [get_ports "LVDS2V5Top6PxSIO"]
#set_property PACKAGE_PIN "L7" [get_ports "LVDS2V5Top6NxSIO"]
#set_property PACKAGE_PIN "N8" [get_ports "LVDS2V5Top5PxSIO"]
#set_property PACKAGE_PIN "P8" [get_ports "LVDS2V5Top5NxSIO"]
#set_property PACKAGE_PIN "M8" [get_ports "LVDS2V5Top4PxSIO"]
#set_property PACKAGE_PIN "M7" [get_ports "LVDS2V5Top4NxSIO"]
#set_property PACKAGE_PIN "L6" [get_ports "LVDS2V5Top3PxSIO"]
#set_property PACKAGE_PIN "M6" [get_ports "LVDS2V5Top3NxSIO"]
#set_property PACKAGE_PIN "J7" [get_ports "LVDS2V5Top2PxSIO"]
#set_property PACKAGE_PIN "J6" [get_ports "LVDS2V5Top2NxSIO"]
#set_property PACKAGE_PIN "J5" [get_ports "LVDS2V5Top1PxSIO"]
#set_property PACKAGE_PIN "K5" [get_ports "LVDS2V5Top1NxSIO"]
#set_property PACKAGE_PIN "J2" [get_ports "LVDS2V5Top0PxSIO"]
#set_property PACKAGE_PIN "J1" [get_ports "LVDS2V5Top0NxSIO"]
# Bottom (bank 34)
#set_property PACKAGE_PIN "N6" [get_ports "LVDS2V5Bottom7PxSIO"]
#set_property PACKAGE_PIN "N5" [get_ports "LVDS2V5Bottom7NxSIO"]
#set_property PACKAGE_PIN "P6" [get_ports "LVDS2V5Bottom6PxSIO"]
#set_property PACKAGE_PIN "P5" [get_ports "LVDS2V5Bottom6NxSIO"]
#set_property PACKAGE_PIN "R5" [get_ports "LVDS2V5Bottom5PxSIO"]
#set_property PACKAGE_PIN "R4" [get_ports "LVDS2V5Bottom5NxSIO"]
#set_property PACKAGE_PIN "R3" [get_ports "LVDS2V5Bottom4PxSIO"]
#set_property PACKAGE_PIN "R2" [get_ports "LVDS2V5Bottom4NxSIO"]
#set_property PACKAGE_PIN "P3" [get_ports "LVDS2V5Bottom3PxSIO"]
#set_property PACKAGE_PIN "P2" [get_ports "LVDS2V5Bottom3NxSIO"]
#set_property PACKAGE_PIN "N1" [get_ports "LVDS2V5Bottom2PxSIO"]
#set_property PACKAGE_PIN "P1" [get_ports "LVDS2V5Bottom2NxSIO"]
#set_property PACKAGE_PIN "N4" [get_ports "LVDS2V5Bottom1PxSIO"]
#set_property PACKAGE_PIN "N3" [get_ports "LVDS2V5Bottom1NxSIO"]
#set_property PACKAGE_PIN "M2" [get_ports "LVDS2V5Bottom0PxSIO"]
#set_property PACKAGE_PIN "M1" [get_ports "LVDS2V5Bottom0NxSIO"]
##### RGB LEDs (banks 34 and 13) #####
# LED1_2V5_R_o (bank 34)
set_property PACKAGE_PIN L2 [get_ports Led12V5RxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led12V5RxSO]
# LED1_2V5_G_o (bank 34)
set_property PACKAGE_PIN L1 [get_ports Led12V5GxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led12V5GxSO]
# LED1_2V5_B_o (bank 34)
set_property PACKAGE_PIN R8 [get_ports Led12V5BxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led12V5BxSO]
# LED2_2V5_R_o (bank 13)
set_property PACKAGE_PIN T16 [get_ports Led22V5RxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led22V5RxSO]
# LED2_2V5_G_o (bank 13)
set_property PACKAGE_PIN U16 [get_ports Led22V5GxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led22V5GxSO]
# LED2_2V5_B_o (bank 13)
set_property PACKAGE_PIN AA20 [get_ports Led22V5BxSO]
set_property IOSTANDARD LVCMOS25 [get_ports Led22V5BxSO]
##### Self reset (bank 34) #####
set_property PACKAGE_PIN H8 [get_ports SelfRstxRNO]
set_property IOSTANDARD LVCMOS25 [get_ports SelfRstxRNO]
##### Clock dedicated pins (Multi-region) #####
# Bank 35
#set_property PACKAGE_PIN "D5" [get_ports "PLLClk2V5LocalPxCI"]
#set_property PACKAGE_PIN "C4" [get_ports "PLLClk2V5LocalNxCI"]
#set_property PACKAGE_PIN "B4" [get_ports "PLLClk2V5NorthPxCI"]
#set_property PACKAGE_PIN "B3" [get_ports "PLLClk2V5NorthNxCI"]
# Bank 34
#set_property PACKAGE_PIN "T2" [get_ports "PLLClk2V5TopxCI"]
#set_property PACKAGE_PIN "L5" [get_ports "PLLClk2V5BottomxCI"]
# Bank 13
#set_property PACKAGE_PIN "Y14" [get_ports "PLLClk2V5SouthPxCI"]
#set_property PACKAGE_PIN "Y15" [get_ports "PLLClk2V5SouthNxCI"]
#set_property PACKAGE_PIN "Y18" [get_ports "Clk2V5RecoveryPxCO"]
#set_property PACKAGE_PIN "Y19" [get_ports "Clk2V5RecoveryNxCO"]
##### Clock dedicated pins (Single-region) #####
# Bank 35
#set_property PACKAGE_PIN "C6" [get_ports "Clk2V5NorthPxCI"]
#set_property PACKAGE_PIN "C5" [get_ports "Clk2V5NorthNxCI"]
#set_property PACKAGE_PIN "D3" [get_ports "Clk2V5WestPxCI"]
#set_property PACKAGE_PIN "C3" [get_ports "Clk2V5WestNxCI"]
# Bank 34
#set_property PACKAGE_PIN "K4" [get_ports "Clk2V5TopPxCI"]
#set_property PACKAGE_PIN "K3" [get_ports "Clk2V5TopNxCI"]
#set_property PACKAGE_PIN "U2" [get_ports "Clk2V5BottomPxCI"]
#set_property PACKAGE_PIN "U1" [get_ports "Clk2V5BottomNxCI"]
# Bank 13
#set_property PACKAGE_PIN "AA14" [get_ports "Clk2V5SouthPxCI"]
#set_property PACKAGE_PIN "AA15" [get_ports "Clk2V5SouthNxCI"]
#set_property PACKAGE_PIN "AA16" [get_ports "Clk2V5EastPxCI"]
#set_property PACKAGE_PIN "AA17" [get_ports "Clk2V5EastNxCI"]
##### Clock outputs #####
## Bank 35
#set_property PACKAGE_PIN "F7" [get_ports "Clk2V5NorthPxCO"]
#set_property PACKAGE_PIN "E7" [get_ports "Clk2V5NorthNxCO"]
#set_property PACKAGE_PIN "F5" [get_ports "Clk2V5WestPxCO"]
#set_property PACKAGE_PIN "E5" [get_ports "Clk2V5WestNxCO"]
# Bank 34
#set_property PACKAGE_PIN "P7" [get_ports "Clk2V5TopPxCO"]
#set_property PACKAGE_PIN "R7" [get_ports "Clk2V5TopNxCO"]
#set_property PACKAGE_PIN "M4" [get_ports "Clk2V5BottomPxCO"]
#set_property PACKAGE_PIN "M3" [get_ports "Clk2V5BottomNxCO"]
# Bank 13
#set_property PACKAGE_PIN "AB16" [get_ports "Clk2V5SouthPxCO"]
#set_property PACKAGE_PIN "AB17" [get_ports "Clk2V5SouthNxCO"]
#set_property PACKAGE_PIN "AB21" [get_ports "Clk2V5EastPxCO"]
#set_property PACKAGE_PIN "AB22" [get_ports "Clk2V5EastNxCO"]
############################################################################
# Other constraints #
############################################################################
##### Operating conditions (for XPE report) #####
# Extended grade (as for -2 speed grade) and maximum consumption estimation
set_operating_conditions -grade extended -process maximum
# 4'' by 4'' PCB, no heatsink, no air flow
set_operating_conditions -airflow 0 -heatsink none -board small
designs/vivado/scalp_router_firmware/2020.2/src/constrs/timing_constraints.xdc 0 → 100644
+ 36
− 0
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############################################################################
# Timing constraints #
############################################################################
##### PS_CLK (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_ports PSClkxCIO]
##### GTP reference clocks (125 MHz) #####
create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk0PxCI]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets GTPRefClk1xC]
##### Clocks from PLLs (125 MHz) #####
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Local}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_North}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_South}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Top}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {PLL_Clk_in_Bottom}]
##### Clocks from neighbours (125 MHz) #####
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_North}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_South}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_East}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_West}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Top}]
#create_clock -period 8.000 -waveform {0.000 4.000} [get_nets {Clk_in_Bottom}]
designs/vivado/scalp_router_firmware/2020.2/src/hdl/reset_delay_gen.vhd 0 → 100644
+ 68
− 0
View file @ 218bad77
----------------------------------------------------------------------------------
-- _ _
-- | |_ ___ _ __(_)__ _
-- | ' \/ -_) '_ \ / _` |
-- |_||_\___| .__/_\__,_|
-- |_|
--
----------------------------------------------------------------------------------
--
-- Company: hepia
-- Author: Joachim Schmidt <joachim.schmidt@hesge.ch>
--
-- Module Name: reset_delay_gen - behavioral
-- Target Device: SCALP xc7z015clg485-2
-- Tool version: 2020.2
-- Description: Reset Delay Generator
--
-- Last update: 2020-10-12
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity reset_delay_gen is
generic (
C_TICKS : integer := 10);
port (
ClkxCI : in std_ulogic;
PllLockedxSI : in std_ulogic;
ResetxRI : in std_ulogic;
ResetDelayedxRO : out std_ulogic);
end entity reset_delay_gen;
architecture behavioral of reset_delay_gen is
-- Signals
signal ResetDelayxRD : std_ulogic_vector((C_TICKS - 1) downto 0) := (others => '1');
begin -- architecture behavioral
-- Asynchronous statements
ResetDelayedxAS : ResetDelayedxRO <= ResetDelayxRD(C_TICKS - 1);
-- Synchronous statements
ResetDelayGenxP : process (ClkxCI) is
begin -- process ResetDelayGenxP
if rising_edge(ClkxCI) then
if PllLockedxSI = '0' then
ResetDelayxRD <= (others => '1');
elsif PllLockedxSI = '1' then
ResetDelayxRD <= ResetDelayxRD((C_TICKS - 2) downto 0) & ResetxRI;
end if;
end if;
end process ResetDelayGenxP;
end architecture behavioral;
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