- Mar 24, 2025
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sebastie.gendre authored
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- Mar 22, 2025
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sebastie.gendre authored
So, any address received on AXI side greater than 255 will be see its MSB truncated. So, 256 will be 0, etc
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sebastie.gendre authored
When address width is lower than 32 bits (set with generic C_DATA_WIDTH): The address transferred from AXI interface to registers bank is truncated. The AXI interface will remove MSB so the address received on AXI side could correspond to an internal register of registers bank
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- Mar 20, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
- Mar 19, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 15, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 14, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 13, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 12, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 10, 2025
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sebastie.gendre authored
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sebastie.gendre authored
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- Mar 09, 2025
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sebastie.gendre authored
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sebastie.gendre authored